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Discussion Groups | FPGA-CPU | help req for 16bit cpu, organization issues
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
help req for 16bit cpu, organization issues - umairsiddiqui0800 - Dec 26 22:05:00 2004
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while trying to make a 16-bit CPU core, I'm facing a dead-on arrival situation! CPU is required to drive mini-UART (by Mr. Ovidiu Lupas, OpenCores. org) on spartan-3 starter kit (to do something ??? - printing "hello world" :-( ). for this system, I was thinking that CPU on power-up/reset draw the user-data/code from platform flash and load into SRAM. Alas! my comp-arch and digital design knowledge proved to be worse than I thought. please help me in further design simplification and any organizational/arch flaw removal, so I end up with something simple and something which could be called "general purpose CPU" - able to do some data processing and controlling...drive a system like system6801 (by Mr. John Kent). after wastage of a lot of time, I come up with: -16 bit datapath -64k flat addressable memory (for both code and data) without paging and segmentation -using word(16bit) addresses, sequential memory words differ by 1 rather than 2. -16 interrupts -separate I/O address space (256 locs) -4k stack -user visible registers: *Accumulator (A) - 16bit *Base/Index (B) - 16bit *loop Counter(C) - 16bit *Stack Pointer(SP) - 12bit *Stack Frame Pointer(FP) - 12bit -overall memory map: *first 16 locs for interrupts - int 0 for reset *last 4k for stack (first 4bits of SP and FP are '1111') *user code/data and memory mapped I/O in between -addressing modes: *register (example: mov A,C) *direct (example: mov A,[16bit absolute address]; *indirect(example: mov A,[B]) *index/base (example: mov A,[B][16bit displacement]; *immediate *within stack (example - accessing args and locals variables: mov A, [fp + 1]; there is no "segment overriding", sp and fp are just for stack management) -jumps, conditional jumps and call are all absolute and supporting all addressing modes (except stack!) -no multiplication, division and barrel shifting although the whole processor seem to be a problem but: -a flat addressable 64k*16 RAM -"using word(16bit) addresses, sequential memory words differ by 1 rather than 2" -fixed stack (I'm so nervous - I could not find datasheets,arch and asm docs for 6502, 6800, 6809 and 68k) -stack size and size of SP and FP, I was trying to avoid stack and code overlap -index/base addressing mode is necessary for array/lut processing (but complicating design), any alternative? I like KISS methodology but my experience is limited to 8088, 8051... Reducing datapath to 8-bit may beautify the design...wide data paths require elegant solutions, which I can't afford! |
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