Sign in

username:

password:



Not a member?

Search fpga-cpu



Search tips

Subscribe to fpga-cpu



fpga-cpu by Keywords

Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A

Discussion Groups

Discussion Groups | FPGA-CPU | simulation libraries

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

simulation libraries - Rob Finch - Jan 1 2:30:00 2005



I'm trying to simulate a design and I need the Xilinx block ram
instances and CLKDLL to simulate. But they aren't included in
ModelSim by default. I tried to add the libraries from the Xilinx
directory, but the OK button in the ModelSim add library dialog is
greyed out. Does this mean I can't simulate these components in
(free) ModelSim ? Or what do I have to do to be able to simulate
these instances ?

Thanks,
Rob




(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Re: simulation libraries - Author Unknown - Jan 1 15:27:00 2005

Maybe a silly answer, but... Did you compile the unisim and/or
simprim ilbraries with xilinx\bin\nt\compxlib? My brother was doing
simulation with the free ModelSim and I think he had no problem with
(inferred from arrays) BRAMs. ModelSim XE is not supported by
compxlib, but I think it usually works.

Regards,
Miguel. To:
From: "Rob Finch" <>
Date sent: Sat, 01 Jan 2005 07:30:34 -0000
Send reply to:
Subject: [fpga-cpu] simulation libraries >
> I'm trying to simulate a design and I need the Xilinx block ram
> instances and CLKDLL to simulate. But they aren't included in
> ModelSim by default. I tried to add the libraries from the Xilinx
> directory, but the OK button in the ModelSim add library dialog is
> greyed out. Does this mean I can't simulate these components in
> (free) ModelSim ? Or what do I have to do to be able to simulate
> these instances ?
>
> Thanks,
> Rob




(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Re: simulation libraries - Nat Chan - Jan 1 21:50:00 2005


Hi,

The Xilinx answer record #12628 summarizes the different things you
would need to do to compile/update HDL simulation libraries, depending
on what your needs are

Answer to "Simulation Libraries - How do I compile and update the
Xilinx HDL simulation libraries? When do I need to update the
simulation libraries?" is at:
http://support.xilinx.com/xlnx/xil_ans_display.jsp
?iLanguageID=1&iCountryID=1&getPagePath=12628

Then if you're going to be doing Microblaze stuff too, answer record
#18386 pertains to EDK simulation libraries & compedklib. Answer to
"6.1 Compedklib - How do I compile the behavioral models for EDK
Simulation in EDK 6.1?" is at:
http://support.xilinx.com/xlnx/xil_ans_display.jsp
?iLanguageID=1&iCountryID=1&getPagePath=18386

Happy New Year,
Nathalie

--- In , "Rob Finch" <robfinch@s...> wrote:
>
> I'm trying to simulate a design and I need the Xilinx block ram
> instances and CLKDLL to simulate. But they aren't included in
> ModelSim by default. I tried to add the libraries from the Xilinx
> directory, but the OK button in the ModelSim add library dialog is
> greyed out. Does this mean I can't simulate these components in
> (free) ModelSim ? Or what do I have to do to be able to simulate
> these instances ?
>
> Thanks,
> Rob





(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )