This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Simon said: > I've bought one of the BurchED > kits so I've got my hands on a (cheap :-) spartan-2 Gee, I hadn't heard of them before. Those kits look pretty attractive! http://www.burched.com.au/index.html I've been less than totally thrilled with my Insight Spartan-II Development Kit: http://www.insight-electronics.com/solutions/kits/xilinx/spartan-ii.html The lack of ground pins on the connectors has been noted on this list before. I spend Friday night tracking down and removing a bad zener diode on the RS-232 interface before I could get it working. Not a good use of time. Simon, do those cable connectors include plenty of ground pins, and some power? I'll post some memory models in the following email. --Mike |
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Mike wrote: > > Simon, do those cable connectors include plenty of ground pins, and > some power? The pin layout is roughly 8 x 20-pin (2x10) headers, and each of the 20-pin headers has access to at least one GND and +5V. On one side there are lots more GND pins (I guess they ran put of S2 pins :-) There was some discussion about them around November on the comp.arch.fpga newsgroup. There was a question over why they only come shipped with 24MHz oscillators, and the answer was basically because that's what Tony had lying around. It's socketed anyway so you can upgrade the clock. Construction is pretty good - all well labelled and it survived the trip halfway around the world to the UK, so I guess they're robust too :-) I even sprung for the IO module (you get 2xRS232, mouse, keyboard (AT,PS2), VGA with a nice IDC header connector. You can probably tell I am reasonably impressed :-) > I'll post some memory models in the following email. Cheers :-) |
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Thanks, Simon. That BurchED Spartan-II kit and accessories would be an attractive platform for my version of Jan Gray's xr16, which I've written from a 'clean sheet of paper' in synthesizable Verilog. The CPU, with a small BlockRAM main memory, a parallel port and a simple UART is currently at 365 slices, which is 30% of my XC2S100. With automatic synthesis and placement (Student Edition 2.1i) it's at a little better than 40 MHz. I'm currently debugging the UART, and then I'll put it all up on my web site for free non-commercial use. Next I'll write a little hex debugger, and then a little self-contained logic analyzer controlled by the CPU and used thru the serial port. As for your other memory model needs, I don't have Jan's gr0000 stuff, so I don't have his ram16x16d. Let's wait for Jan to respond. --Mike |