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Discussion Groups | FPGA-CPU | Catenation operator - another dumb question :-)

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Catenation operator - another dumb question :-) - Author Unknown - Feb 6 16:40:00 2001


Could anyone tell me if the catenation operator {,,...} can
be used on the LHS of an assignment ?

The lines below (almost verbatim from the gr0000 module) won't
synthesise in Webpack ...

// Adder and subtractor section.
wire [`N:0] sum;
wire add = ~(`ALU&(`SUB|`SBC|`CMP));
reg c;
wire ci = add ? c : -c;
wire co;
wire x;

{co, sum, x} = add ? {a,ci} + {b,1'b1}
: {a,ci} - {b,1'b1};

My (completely naive) understanding of that is that the correct
branch will be taken according to 'add', and the `N+2 bit result
will be apportioned as 1-bit to 'co', 'N bits to 'sum', and 1 bit
to 'x' in that order.

Unfortunately the synthesis tool doesn't agree :-( I get a parse
error on the {,,} line. On a different note, is the synthesis tool in
Webpack worth using ? I have a copy of foundation 2.1i which came
with an XESS board, if that's better ? Of course, having written
*that* sentence, it'll be some really obvious sybtax error :-)

BTW, I'm not sure if this really falls under the remit of this group -
feel free to tell me to go to comp.lang.verilog if that's more
appropriate :-)

ATB,
Simon




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RE: Catenation operator - another dumb question :-) - Jan Gray - Feb 7 3:24:00 2001

Hmm. I don't know if it *is* valid Verilog. (I suppose I need to invest in
a Verilog language reference manual.) It is accepted by Synplify and
Veriwell however.

(BTW I just love to write shift registers as
always @(posedge clk) {f,e,d,c,b,a} <= {e,d,c,b,a,in};
)

I think a simple workaround would be to write
wire [17:0] co_sum_x = add ? ... : ... ;
co = co_sum_x[17];
sum = co_sum_x[16:1];
x = co_sum_x[0];

The purpose here is to
1) inject the carry-in,
2) capture the carry-out,
3) add or subtract the two operands and
4) help the synthesis tool synthesize an ADD-SUB structure in one column of
LUTs.

I wouldn't be surprised if some synthesis tools fail to do (4) but succeed
if you feed them an
if (add)
co_sum_x = ...;
else
co_sum_x = ...;
Trying to write Verilog that synthesizes efficiently (or at all) under
multiple synthesis tools turns the "pushing on a rope" problem into "pushing
on four ropes simultaneously"!

Sorry, I haven't tried the WebPack tools. (Does anyone know if they
can/can't co-exist with an Alliance 3.x tools installation?)

Jan Gray, Gray Research LLC




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WebPack and Alliance (was Re: Catenation operator ...) - Author Unknown - Feb 7 21:41:00 2001

--- In fpga-cpu@y..., "Jan Gray" <jsgray@a...> wrote:
>
> Sorry, I haven't tried the WebPack tools. (Does anyone know if they
> can/can't co-exist with an Alliance 3.x tools installation?) I'm running two machines with both Webpack and Alliance:

work: Win '98, Alliance Standard 3.3i(sic) SP6, Webpack 3.2

home: Win '95, Alliance Base 2.1i SP6, Webpack 3.2

So far, no problems; I'm running only the WebPack FPGA
implementation flow, not any of the other plug-ins.

The WebPack installs into a separate directory by default,
and seems to leave the Alliance Xilinx path/variable settings
alone. I believe there's some info. on the Xilinx Webpack FAQ
or support web pages about running WebPack with other Xilinx S/W.

( I haven't installed Alliance 3.x on the '95 machine, as I
recall seeing some "it'll never work" messages somewhere on the
Xilinx website; although the requirements for Webpack also
list Win '98, I've experienced no problems under '95 yet... ) WebPack notes:

- includes neither XDL nor FPGA Editor; when the tools have
bugs, the usual find-it-and-fix-it methods aren't available
( unless you happen to own some other Xilinx S/W )

- includes only the JTAG download tool, not the HW debugger Brian



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