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Discussion Groups | FPGA-CPU | RE: Re: why FPGA?

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

RE: Re: why FPGA? - Austin Franklin - Jan 13 12:42:00 2005

Hi Peter,

> A bus on a real circuit card and with real connectors will have
> signal-signal
> capacitance, this is guaranteed.

My point was, there is nothing in the PCI spec that covers this signal to
signal capacitance.

> Signal-signal crosstalk is
> worse with high
> source impedances - hence - a signal integrity issue.

I don't agree that adding a series resistor is guaranteed to cause a "signal
integrity issue" in this case.

> Its not the
> clock rate
> thats an issue here either, its the edge rate.

Clock rate can be governed by slew/edge rate. Adding a resistor to a signal
increases the slew rate, and therefore decreases the operating frequency.
You won't make set-up and hold timing. IF you decrease the frequency, you
therefore increase the set-up time, which, if the clock rate is slow enough,
will make you within spec. So, my point was, that this (issue) is not a
signal integrity issue, but a timing issue. Impedance and cross-talk may
very well be an issue, but they are a different issue, and may or may not be
a problem, and may easily be overcome, but timing is guaranteed to be a
problem, and can only be overcome by decreasing the frequency.

Regards,

Austin




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