This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Austin- > You're welcome. Keep the trace length between the switches and the IC the > shortest you can, and choose your switches wisely ;-) If you are pinning > for an FPGA, make sure your FPGA pinout optimizes the routing...and also I'd > suggest routing on the outer layers only (minimizing vias, such that you > have none on the top layer, and only one to get to the bottom layer) and > making sure you watch your trace characteristic impedance (which for PCI is > 60-100 ohms...and get a copy of the PCI spec and look over the routing > section for trace lengths etc.), which means you (or your PCB fabricator) > have to calculate the trace widths, and make sure the PCB manufacturer knows > what they are when you order the boards, in fact, I'd suggest asking them to > work up a stack-up for you prior to PCB layout. > > Please feel free to ask me questions with regards to the PCI aspect of this > if you have any. What do you think about this one: http://www.fairchildsemi.com/ds/FS/FSTD32211.pdf That does most of the work in 16 x 5.5 mm. 48 bits is enough if I use the series R method on slow signals, for example PME, CLKRUN, and RST. Does that sound at least close to being legit? > P.S. BTW, are you making a 5V only, or a "universal" card (3.3V and 5V)? If > a universal card, there are other issues you may want to be aware of. Normally it's supposed to be a 3.3V only card. There are some times though when it has to drop into a 5V desktop PC environment. Grrr. -Jeff |