This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Austin- > You're welcome. Keep the trace length between the switches and the IC the > shortest you can, and choose your switches wisely ;-) If you are pinning > for an FPGA, make sure your FPGA pinout optimizes the routing...and also I'd > suggest routing on the outer layers only (minimizing vias, such that you > have none on the top layer, and only one to get to the bottom layer) and > making sure you watch your trace characteristic impedance (which for PCI is > 60-100 ohms...and get a copy of the PCI spec and look over the routing > section for trace lengths etc.), which means you (or your PCB fabricator) > have to calculate the trace widths, and make sure the PCB manufacturer knows > what they are when you order the boards, in fact, I'd suggest asking them to > work up a stack-up for you prior to PCB layout. > > Please feel free to ask me questions with regards to the PCI aspect of this > if you have any. What do you think about this one: http://www.fairchildsemi.com/ds/FS/FSTD32211.pdf That does most of the work in 16 x 5.5 mm. 48 bits is enough if I use the series R method on slow signals, for example PME, CLKRUN, and RST. Does that sound at least close to being legit? > P.S. BTW, are you making a 5V only, or a "universal" card (3.3V and 5V)? If > a universal card, there are other issues you may want to be aware of. Normally it's supposed to be a 3.3V only card. There are some times though when it has to drop into a 5V desktop PC environment. Grrr. -Jeff |
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Possibly of interest to this group:
http://www.eedesign.com/news/showArticle.jhtml?articleID=57701852 SAN JOSE, Calif. — British EDA startups Orange Tree Technologies and SystemCrafter have teamed to make SystemC synthesis more affordable for the masses. The partners have jointly introduced a bundle for programming FPGAs based on the SystemC language. The bundle consists of a new SystemC-to-VHDL compiler called SystemCrafter SC from SystemCrafter and an FPGA development board called ZestSC1 from Orange Tree Technologies. According to the companies, SystemCrafter SC automatically synthesizes hardware designs written in SystemC to VHDL, which in turn can be used with commonly available tools to target Xilinx FPGAs. This, according to the companies, allows engineers and programmers to design, debug and simulate hardware and systems using their existing C++ development environment. The companies said that where most other SystemC and proprietary C-to-hardware tools cost tens of thousand of dollars, often for just a one-year subscription, SystemCrafter SC costs $995 for a perpetual license for the compiler alone, or $1,490, when bundled with the ZestSC1 development board. SystemCrafter SC allows users to control scheduling and allocation. The same SystemC testbench can be used to verify the design at all stages, the companies said. Simulation can be performed with a standard C++ compiler and free class libraries from the Open SystemC Initiative, the companies said. ZestSC1 is a desktop FPGA development board with high speed 480Mbits/s USB interface, 8 Mbytes of SRAM and a Xilinx Spartan-3 FPGA with 1 million logic gates, which can be programmed by the compiler. The package can be purchased direct from the SystemCrafter Web site. A free evaluation version of SystemCrafter SC can be downloaded and used for 30 days. [Non-text portions of this message have been removed] |
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--- In , Mike Cheponis <mac@N...> wrote: > Possibly of interest to this group: > ZestSC1 is a desktop FPGA development board with high speed 480Mbits/s USB interface, 8 Mbytes of SRAM and a Xilinx Spartan-3 FPGA with 1 million logic gates, which can be programmed by the compiler. WOW, anybody know where they got the 8 MByte SRAM from ? |