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Discussion Groups | FPGA-CPU | OT: verilog arrays

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

OT: verilog arrays - Rob Finch - Jan 22 16:53:00 2005


Does anyone know how to pass arrays to a module in Verilog ? I tried
this as a test but it doesn't work:

module arrayTest(s, a, o);
input [2:0] s;
input [3:0] a [4:0]; // this line cause the synthesizer to
croak with an error 'expecting ; not [ '
output [3:0] o;

assign o = a[s];

endmodule please don't tell me I have to split the array into individual pieces
and go a0, a1, a2, a3, etc.....





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Re: OT: verilog arrays - Ed Corter - Jan 23 3:40:00 2005


RE:

module arrayTest(s, a, o);
input [2:0] s;
input [3:0] a;
output [3:0] o;

assign o = { a[0], s[2:0] };

or bitwise

assign o = { a[0], a[2], a[4], s[0] }; also use this for writing a shift register
personally I would define O as a registered output or define it as a wire

I.E.

wire [3:0] 0;
---------------------------------




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Re: OT: verilog arrays - Paul Davis - Jan 23 10:38:00 2005

Rob Finch wrote:

> please don't tell me I have to split the array into individual pieces
> and go a0, a1, a2, a3, etc.....

You have to split the array into individual pieces and go a0, a1, a2,
a3, etc. :)

Seriously, it can't be done in Verilog. You can do it in SystemVerilog,
if you can find a SystemVerilog compiler.

The usual Verilog fix is to create a port with n*m bits, and index into
it, but this can be tricky; you should find multiple Google hits on
compl.lang.verilog.

Of course, you could always use just VHDL instead.




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