Request for comments: 16-bit cpu arch | FPGA-CPU

Require comments on given instruction set (cheated from many areas - including Hennessy & Patterson comp arch book)for datapath *simplificaton* and less clock-cylces: -number of registers, r0 utilization -size of addressable memory -dealing unaligned bytes? -addressing modes, especially implementation of register-indirect addressing and absolute addressing -recommended "displacement" (no. of bits)for data(base-displacement loading) and code(jumps)? should both be equal(keeping *simplificaton* in mind)? -"good algorithm(s)" for assigning opcodes -any (additional) instruction for bus and cpu control (DMA not required) -any other "highly recomended" instruction/feature... thankyou... /////////////////////////////////////////////////////////////////////////////////////// 1) Total 64k addressable memory: 2^16 (0 to 2^16 - 1) linear and byte-addressable memory locations 2) 8 general purpose registers (r0, r1 ... r6, sp), sp should not be used for any purpose except for stack(present in memory) manipulation, r0 hardwired zero? 3) Memory mapped I/O 4) 16-bit PC 5) FLAGS[CF,ZF,SF,IF,OF,00000000000] 6) 16 vector interrupts (0-reset,1-invalid instruction,2-arithmatic overflow, rest masked) 7) support 8-bit operands for loading/storing 8) 16-bit operands aligned on even boundary (how to deal unaligned bytes?) 9) Addressing modes: register addressing, base displacement addressing, immediate addressing, register-indirect addressing (could be implemented by 0 as displacement in base displacement addressing?) and absolute addressing (could be implemented by r0 as base in base displacement addressing?) 10) All instructions should be either 16/32-bits (16-bit prefered) 11) Caching, Pipelining, Paging and DMA not required Instruction Mov reg16,reg16 Lw / Mov reg16,[reg16] Lw / Mov reg16,(addr) Lw / Mov reg16,[reg16+disp] Lwi / Mov reg16,imm16 Swi / Mov [reg16],imm16 Swi / Mov (addr),imm16 Swi / Mov [reg16+disp],imm16 Sw / Mov [reg16],reg16 Sw / Mov (addr),reg16 Sw / Mov [reg16+disp],reg16 Lbu / Movzx reg16,[reg16] Lbu / Movzx reg16,(addr) Lbu / Movzx reg16, [reg16 + disp] Sbu / Movzx [reg16],reg16 Sbu / Movzx (addr),reg16 Sbu / Movzx [reg16+disp],reg16 Lb / Movsx reg16,[reg16] Lb / Movsx reg16,(addr) Lb / Movsx reg16, [reg16 + disp] Sb / Movsx [reg16],reg16 Sb / Movsx (addr),reg16 Sb / Movsx [reg16+disp],reg16 Push reg16 Push [reg16] Push (addr) Push [reg16+disp] Pop reg16 Pop [reg16] Pop (addr) Pop [reg16+disp] Pushf Popf Add reg16,reg16 Add reg16,[reg16] Add reg16,(addr) Add reg16,[reg16+disp] Add reg16,imm16 Add [reg16],imm16 Add (addr),imm16 Add [reg16+disp],imm16 Add [reg16],reg16 Add (addr),reg16 Add [reg16+disp],reg16 Sub reg16,reg16 Sub reg16,[reg16] Sub reg16,(addr) Sub reg16,[reg16+disp] Sub reg16,imm16 Sub [reg16],imm16 Sub (addr),imm16 Sub [reg16+disp],imm16 Sub [reg16],reg16 Sub (addr),reg16 Sub [reg16+disp],reg16 Adc reg16,reg16 Adc reg16,[reg16] Adc reg16,(addr) Adc reg16,[reg16+disp] Adc reg16,imm16 Adc [reg16],imm16 Adc (addr),imm16 Adc [reg16+disp],imm16 Adc [reg16],reg16 Adc (addr),reg16 Adc [reg16+disp],reg16 Sbb reg16,reg16 Sbb reg16,[reg16] Sbb reg16,(addr) Sbb reg16,[reg16+disp] Sbb reg16,imm16 Sbb [reg16],imm16 Sbb (addr),imm16 Sbb [reg16+disp],imm16 Sbb [reg16],reg16 Sbb (addr),reg16 Sbb [reg16+disp],reg16 Inc reg16 Inc [reg16] Inc (addr) Inc [reg16+disp] Dec reg16 Dec [reg16] Dec (addr) Dec [reg16+disp] Neg reg16 Neg [reg16] Neg (addr) Neg [reg16+disp] Cmp reg16,reg16 Cmp reg16,[reg16] Cmp reg16,(addr) Cmp reg16,[reg16+disp] Cmp reg16,imm16 Cmp [reg16],imm16 Cmp (addr),imm16 Cmp [reg16+disp],imm16 Cmp [reg16],reg16 Cmp (addr),reg16 Cmp [reg16+disp],reg16 Test reg16,reg16 Test reg16,[reg16] Test reg16,(addr) Test reg16,[reg16+disp] Test reg16,imm16 Test [reg16],imm16 Test (addr),imm16 Test [reg16+disp],imm16 Test [reg16],reg16 Test (addr),reg16 Test [reg16+disp],reg16 And reg16,reg16 And reg16,[reg16] And reg16,(addr) And reg16,[reg16+disp] And reg16,imm16 And [reg16],imm16 And (addr),imm16 And [reg16+disp],imm16 And [reg16],reg16 And (addr),reg16 And [reg16+disp],reg16 Or reg16,reg16 Or reg16,[reg16] Or reg16,(addr) Or reg16,[reg16+disp] Or reg16,imm16 Or [reg16],imm16 Or (addr),imm16 Or [reg16+disp],imm16 Or [reg16],reg16 Or (addr),reg16 Or [reg16+disp],reg16 Xor reg16,reg16 Xor reg16,[reg16] Xor reg16,(addr) Xor reg16,[reg16+disp] Xor reg16,imm16 Xor [reg16],imm16 Xor (addr),imm16 Xor [reg16+disp],imm16 Xor [reg16],reg16 Xor (addr),reg16 Xor [reg16+disp],reg16 Not reg16 Not [reg16] Not (addr) Not [reg16+disp] Shl/Sal reg16,imm4 Shl/Sal [reg16],imm4 Shl/Sal (addr),imm4 Shl/Sal [reg16+disp] Shr reg16,imm4 Shr [reg16],imm4 Shr (addr),imm4 Shr [reg16+disp],imm4 Sar reg16,imm4 Sar [reg16],imm4 Sar (addr),imm4 Sar [reg16+disp],imm4 Rol reg16,imm4 Rol [reg16],imm4 Rol (addr),imm4 Rol [reg16+disp],imm4 Ror reg16,imm4 Ror [reg16],imm4 Ror (addr),imm4 Ror [reg16+disp],imm4 Rcl reg16,imm4 Rcl [reg16],imm4 Rcl (addr),imm4 Rcl [reg16+disp],imm4 Rcr reg16,imm4 Rcr [reg16],imm4 Rcr (addr),imm4 Rcr [reg16+disp],imm4 Call [reg16] Call (addr) Call [reg16 + disp] Ret Int imm4 Into - overflow int will be called if OF=1 Iret Jmp [reg16] Jmp (addr) Jmp [reg16+disp] Je/Jz disp -- zf=1 Jl/Jnge disp -- sf<>of Jle/Jng disp -- zf=1, sf<>of Jb/Jnae disp -- cf=1 Jbe/Jna disp -- cf=1,zf=1 Jo disp -- of=1 Js disp -- sf=1 Jne/Jnz disp -- zf=0 Jnl/Jge disp -- SF=OF Jnle/Jg disp -- ZF=0, SF=OF Jnb/Jae disp -- Cf=0 Jnbe/Ja disp -- if CF=0,ZF=0 Jno disp -- if OF=0 Jns disp -- if SF=0 Clc Cmc Stc Nop Hlt //////////////////////////////////////////////////////////////////////////////////// __________________________________

(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Sign in

Search fpga-cpu

Subscribe to fpga-cpu

fpga-cpu by Keywords

Ads

Discussion Groups

Discussion Groups | FPGA-CPU | Request for comments: 16-bit cpu arch

Request for comments: 16-bit cpu arch - Umair siddiqui - Feb 8 1:56:00 2005