Recommendation Of Logic Level Translator | FPGA-CPU

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I have just about finished building a 32 channel logic analyzer using a Spartan IIE FPGA. The analyzer works and the VB application is essentially complete. The thing is, I don't want to dedicate my relatively expensive II E to the task. I want to port the application to the Spartan 3 Starter Board. As I understand it, the II E has 5V tolerant inputs with 100 ohm series resistors and that is not true for the Spartan 3. So, I need to change the pod design to use level translation which is a good thing because I want to use the device with both 3.3V and 5V circuits. I have been looking at http://www.fairchildsemi.com/ds/74/74LVXC3245.pdf as one possibility. I like the packaging because I can solder it. I really want to avoid the very high density BGA devices. The fact that the devices are cheap and in stock at DigiKey is another plus! The maximum sampling rate is 40 MHz so the propogation delay doesn't seem out of line. Any thoughts on this?

Re: Recommendation Of Logic Level Translator
Re: Recommendation Of Logic Level Translator

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On Fri, 11 Feb 2005, rtstofer wrote: > > I have just about finished building a 32 channel logic analyzer > using a Spartan IIE FPGA. The analyzer works and the VB application > is essentially complete. The thing is, I don't want to dedicate my > relatively expensive II E to the task. I want to port the > application to the Spartan 3 Starter Board. > > As I understand it, the II E has 5V tolerant inputs with 100 ohm > series resistors and that is not true for the Spartan 3. So, I need > to change the pod design to use level translation which is a good > thing because I want to use the device with both 3.3V and 5V > circuits. > > I have been looking at > http://www.fairchildsemi.com/ds/74/74LVXC3245.pdf as one > possibility. I like the packaging because I can solder it. I > really want to avoid the very high density BGA devices. The fact > that the devices are cheap and in stock at DigiKey is another plus! > > The maximum sampling rate is 40 MHz so the propogation delay doesn't > seem out of line. > > Any thoughts on this? How about using the LVDS inputs single ended with a programmable reference source (filtered PWM) for the other sides, and about a 2/1 resistive divider? That way you protect the inputs, and you get programmable thresholds on your LA... > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links Peter Wallace Mesa Electronics

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Discussion Groups | FPGA-CPU | Recommendation Of Logic Level Translator

Recommendation Of Logic Level Translator - rtstofer - Feb 11 14:27:00 2005

Re: Recommendation Of Logic Level Translator - Eric Smith - Feb 11 14:40:00 2005

Re: Recommendation Of Logic Level Translator - Peter C. Wallace - Feb 11 14:50:00 2005