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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
S3e starter kit - Alex Gibson - Mar 4 21:41:00 2005
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Quarter 3 2005 http://www.xilinx.com/products/spartan3e/s3eboards.htm US$149 Also webpack 7.1 comming soon supposedly including the linux version. S3e chip details http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3E Board details Complete solution, including: * Xilinx Spartan-3E 500,000 gate Platform FPGA XC3S500E-4FG320 * Memory o 32 Mbit Parallel Flash o 8 Mb SPI Flash o 32M-byte of DDR SDRAM * Board Interfaces o Ethernet 10/100 Phy o USB 2.0 Phy+Controller o 3-bit, 8-color VGA display port o 9-pin RS-232 Serial Port o PS/2-style mouse/keyboard port o Three 40-pin expansion connection ports * Additional Features o 2 Line LCD o Four slide switches o Eight individual LED outputs o Two momentary-contact push button switches o 90 MHz crystal clock oscillator o Universal Power Supply 100-240V AC, 50/60Hz** [Non-text portions of this message have been removed] |
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Re: S3e starter kit - rtstofer - Mar 5 2:45:00 2005
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--- In , Alex Gibson <yahoo@a...> wrote: > Quarter 3 2005 > http://www.xilinx.com/products/spartan3e/s3eboards.htm > US$149 That should be fun to play with. I wonder how much the ethernet & USB IPs are going to use. If that could be < 200K gates then there would be room for some serious projects. I'm still considering the 1M gate S3 Starter Board. So many toys, so little time... > Also webpack 7.1 comming soon supposedly including the linux version. I'll be happy if they correct the errors recently added with 6.3.03i. I have to retain 6.2.03i to program CPLDs. |
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Re: Re: S3e starter kit - Alex Gibson - Mar 5 23:09:00 2005
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rtstofer wrote:
>>Also webpack 7.1 comming soon supposedly including the linux >> >> >version. > >I'll be happy if they correct the errors recently added with >6.3.03i. I have to retain 6.2.03i to program CPLDs. > ?? Whats the problem with 6.3 ? We've just put it in all the lab computers Hope we don't have to go and make a new image and reimage them all. Only use the xc9572xl cpld in an introductory subject. Alex [Non-text portions of this message have been removed] |
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Re: Re: S3e starter kit - Jacob Nelson - Mar 5 23:30:00 2005
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6.2i also introduced an annoying synthesis bug in XST with flow-through combinatorial logic in modules. I think it's fixed in 7.1i. jacob On Sun, 6 Mar 2005, Alex Gibson wrote: > rtstofer wrote: > >> >> >> >> >>> Also webpack 7.1 comming soon supposedly including the linux >>> >>> >> version. >> >> I'll be happy if they correct the errors recently added with >> 6.3.03i. I have to retain 6.2.03i to program CPLDs. >> >> >> > ?? Whats the problem with 6.3 ? > > We've just put it in all the lab computers > Hope we don't have to go and make a new image and reimage them all. > > Only use the xc9572xl cpld in an introductory subject. > > Alex > > [Non-text portions of this message have been removed] > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
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Re: Re: S3e starter kit - Jeff Brower - Mar 5 23:47:00 2005
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Jacob- > 6.2i also introduced an annoying synthesis bug in XST with flow-through > combinatorial logic in modules. I think it's fixed in 7.1i. What is Xilinx current version for ISE? I thought it was v6.3, but now I see 7.xx? -Jeff > On Sun, 6 Mar 2005, Alex Gibson wrote: > > > > > rtstofer wrote: > > > >> > >> > >> > >> > >>> Also webpack 7.1 comming soon supposedly including the linux > >>> > >>> > >> version. > >> > >> I'll be happy if they correct the errors recently added with > >> 6.3.03i. I have to retain 6.2.03i to program CPLDs. > >> > >> > >> > > ?? Whats the problem with 6.3 ? > > > > We've just put it in all the lab computers > > Hope we don't have to go and make a new image and reimage them all. > > > > Only use the xc9572xl cpld in an introductory subject. > > > > Alex > > > > > > > > [Non-text portions of this message have been removed] > > > > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > Yahoo! Groups Links > > > > > > > > > > > > > > > > > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
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Re: Re: S3e starter kit - Jeff Brower - Mar 5 23:49:00 2005
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Jacob- > 6.2i also introduced an annoying synthesis bug in XST with flow-through > combinatorial logic in modules. I think it's fixed in 7.1i. What is Xilinx current version for ISE? I thought it was v6.3, but now I see 7.xx. Is that for XST only? -Jeff > On Sun, 6 Mar 2005, Alex Gibson wrote: > > > > > rtstofer wrote: > > > >> > >> > >> > >> > >>> Also webpack 7.1 comming soon supposedly including the linux > >>> > >>> > >> version. > >> > >> I'll be happy if they correct the errors recently added with > >> 6.3.03i. I have to retain 6.2.03i to program CPLDs. > >> > >> > >> > > ?? Whats the problem with 6.3 ? > > > > We've just put it in all the lab computers > > Hope we don't have to go and make a new image and reimage them all. > > > > Only use the xc9572xl cpld in an introductory subject. > > > > Alex > > > > > > > > [Non-text portions of this message have been removed] > > > > > > > > To post a message, send it to: > > To unsubscribe, send a blank message to: > > Yahoo! Groups Links > > > > > > > > > > > > > > > > > > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
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Re: Re: S3e starter kit - Jeff Brower - Mar 6 0:59:00 2005
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Alex- > >What is Xilinx current version for ISE? I thought it was v6.3, but now I see 7.xx. > >Is that for XST only? > > > >-Jeff > > > At the moment just release or just to be released for XST only > > According to a post in comp.arch.fpga webpack 7.1 should be out sometime > this month > message id : <> titled Xilinx 7.1 > > Also 7.1 has a builtin simulator. Back to like 2.1 ? > So don't know if that means no more modelsim ? Ok thanks! We just upgraded to v6.3 so I will go check our XST version. No ModelSim? Not surprising at all. About 5 years ago Xilinx used Aldec's schematic entry, which was very good, then killed it for one of the worst schematic GUIs around. I swear it looked like Lattice's schematic tool at the time, just horrible -- making a connection was not just drawing a line, it was a series of obscure clicks -- so painful. We used to joke that they took a map of existing schematic entries they could buy, and threw a dart at it. A Xilinx FAE at the time explained to me that Xilinx was determined to own their own tools, and I doubt that's changed. Although a quick web search shows there was also litigation involved. Xilinx schematic entry has improved a lot since then, it has become easier to use - and most important -- very reliable, with accurate error reporting. To Xilinx' great credit, they must have bought source code for it, and have shown willingness to go in and work hard to improve it. -Jeff PS. Lest anyone think we do a lot of schematic entry, we use it for top-level only, with no gates or discretes. Being able to see where Verilog blocks fit, and have some general overview of what is system I/O vs. what is internal, is a fantastic documentation value. And being required to compile that picture forces the documentation to stay accurate and up-to-date. |
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Re: Re: S3e starter kit - Alex Gibson - Mar 6 1:01:00 2005
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Jeff Brower wrote: >Jacob- > >>6.2i also introduced an annoying synthesis bug in XST with flow-through >>combinatorial logic in modules. I think it's fixed in 7.1i. >> >> > >What is Xilinx current version for ISE? I thought it was v6.3, but now I see 7.xx. >Is that for XST only? > >-Jeff > At the moment just release or just to be released for XST only According to a post in comp.arch.fpga webpack 7.1 should be out sometime this month message id : <> titled Xilinx 7.1 Also 7.1 has a builtin simulator. Back to like 2.1 ? So don't know if that means no more modelsim ? Alex [Non-text portions of this message have been removed] |
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Re: S3e starter kit - rtstofer - Mar 6 1:42:00 2005
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--- In , Alex Gibson <yahoo@a...> wrote: > rtstofer wrote: > > > > > > > > > > >>Also webpack 7.1 comming soon supposedly including the linux > >> > >> > >version. > > > >I'll be happy if they correct the errors recently added with > >6.3.03i. I have to retain 6.2.03i to program CPLDs. > > > > > > > ?? Whats the problem with 6.3 ? > > We've just put it in all the lab computers > Hope we don't have to go and make a new image and reimage them all. I am using the XC9572 CPLD and programming it with a Cable IV. With 6.3.03 I am not able to program the device. No problem with the XC2S300E or the XC3S200 FPGAs but a huge problem with the CPLD. I looked on the Xilinx site and if I found the right thing, it admitted there was a problem and resolved to fix it in a future release. So, I keep both versions. You mileage may vary... > Only use the xc9572xl cpld in an introductory subject. > > Alex > > [Non-text portions of this message have been removed] |
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Re: Re: S3e starter kit - Alex Gibson - Mar 6 2:25:00 2005
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rtstofer wrote: >I am using the XC9572 CPLD and programming it with a Cable IV. With >6.3.03 I am not able to program the device. No problem with the >XC2S300E or the XC3S200 FPGAs but a huge problem with the CPLD. > >I looked on the Xilinx site and if I found the right thing, it >admitted there was a problem and resolved to fix it in a future >release. > >So, I keep both versions. You mileage may vary... > >>Only use the xc9572xl cpld in an introductory subject. >> >>Alex >> >> >> >> I wanted to stick with 6.2 but got ignored. Don't think anyone tested 6.3. They just went and installed it. Subject labs are only a max of 50 computers but they put it on the default Engineering image so probably around 100+ computers (+ Zenworks framework when Engineering students log in anywhere on the uni network(vpn comming soon - access anywhere over the net)) Thanks Alex |
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Re: Re: S3e starter kit - Alex Gibson - Mar 6 2:47:00 2005
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rtstofer wrote: >>?? Whats the problem with 6.3 ? >> >>We've just put it in all the lab computers >>Hope we don't have to go and make a new image and reimage them all. >> >> >I am using the XC9572 CPLD and programming it with a Cable IV. With >6.3.03 I am not able to program the device. No problem with the >XC2S300E or the XC3S200 FPGAs but a huge problem with the CPLD. > >I looked on the Xilinx site and if I found the right thing, it >admitted there was a problem and resolved to fix it in a future >release. > >So, I keep both versions. You mileage may vary... > You wouldn't have a link ? Going to get our support guys to test the boards in the lab first thing tomorrow. We don't need 300+ students unable to program their boards. Thanks Alex |
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Re: S3e starter kit - rtstofer - Mar 6 4:35:00 2005
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--- In , Alex Gibson <yahoo@a...> wrote: > rtstofer wrote: > > >>?? Whats the problem with 6.3 ? > >> > >>We've just put it in all the lab computers > >>Hope we don't have to go and make a new image and reimage them all. > >> > >> > >I am using the XC9572 CPLD and programming it with a Cable IV. With > >6.3.03 I am not able to program the device. No problem with the > >XC2S300E or the XC3S200 FPGAs but a huge problem with the CPLD. > > > >I looked on the Xilinx site and if I found the right thing, it > >admitted there was a problem and resolved to fix it in a future > >release. > > > >So, I keep both versions. You mileage may vary... > > > You wouldn't have a link ? No, I just searched Xilinx and I can't find it but that doesn't mean much. I had a heck of a time finding it to start with. If I have time I will try to duplicate the error later today. But, my problem is solved. Not very pretty, but solved. You may find that your systems program just fine. But, there is nothing like a test! > > Going to get our support guys to test the boards in the lab first thing > tomorrow. > We don't need 300+ students unable to program their boards. > > Thanks > Alex |
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