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Discussion Groups | FPGA-CPU | Power optimization at Code level?
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Power optimization at Code level? - gutty19 - Mar 27 19:48:00 2005
Hi,
I am concerend more on Virtex fpgas. Are there any special way of
planning the architecture of a fpga design which would reduce the
power consumption (for eg. reducing operating frequency etc.). If
there is some paper/resource available on these tips, it would be
really helpful.
Thanks,
gutty.
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Re: Power optimization at Code level? - Javier Basilio Pérez Ramas - Mar 30 10:50:00 2005
You are thinking about a very interesting question. FPGA based
systems are known for their high power consumption. FPGA providers are
working in order to reduce power cosumption, but the way you choose to
design have something to say.
A simply but efficent method to reduce power consumption is using
chip enable on the flip flops. Simple turn off the CE in the parts of
your design that aren't used in a cycle. For example, in a CPU, it's
hard to find an instruction that uses all the resources at the same
time, such as the multiplier on your ALU. Turning off the CE of the
registers on these parts will reduce power cosumption. Also you can use
resources like the BUFGMUX in the Virtex series to choose a slow clock,
as you workload requieres. Think what parts of the system can work
slower and use a divided clock in them. Use registers: glitches are
power consuming. Design your FSMs carefully to minimize transitions
between states. Don't let unused parts of the system to work if they
aren't needed.
There is some good papers about this; it shouldn't be hard to find
it in the net.
Best regards,
Javier Basilio
gutty19 escribió: >Hi,
>I am concerend more on Virtex fpgas. Are there any special way of
>planning the architecture of a fpga design which would reduce the
>power consumption (for eg. reducing operating frequency etc.). If
>there is some paper/resource available on these tips, it would be
>really helpful.
>Thanks,
>gutty. >
>To post a message, send it to: fpga-cpu@fpga...
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