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Discussion Groups | FPGA-CPU | Use for 2 bit opcode ?
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Use for 2 bit opcode ? - Rob Finch - Apr 2 15:47:00 2005
Can anyone think of a use for a two bit opcode ?
It all started when I decided to use a 42 bit code. Three opcodes are
packed into 128 bits, but that leaves 2 bits left over, so what can I
do with them ?
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Re: Use for 2 bit opcode ? - Rick Collins - Apr 2 16:13:00 2005
--- In fpga-cpu@fpga..., "Rob Finch" <robfinch@s...> wrote:
>
> Can anyone think of a use for a two bit opcode ?
>
> It all started when I decided to use a 42 bit code. Three opcodes
are
> packed into 128 bits, but that leaves 2 bits left over, so what can
I
> do with them ?
Sure, there are at least two things I could suggest. One is to use
them as if they were full opcodes but with the remaining 40 bits fixed
at 0 or some other value. Or you can pick your three most commonly
used opcodes (along with NOP) and map them to those. This will let
you pack 4 instructions in the 128 bit word in those cases.
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Re: Use for 2 bit opcode ? - Leon Heller - Apr 2 16:17:00 2005
----- Original Message -----
From: "Rob Finch" <robfinch@robf...>
To: <fpga-cpu@fpga...>
Sent: Saturday, April 02, 2005 8:47 PM
Subject: [fpga-cpu] Use for 2 bit opcode ? >
>
> Can anyone think of a use for a two bit opcode ?
>
> It all started when I decided to use a 42 bit code. Three opcodes are
> packed into 128 bits, but that leaves 2 bits left over, so what can I
> do with them ?
Lisp machines had tag bits, perhaps you can use them for something similar.
Leon
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
From: "Rob Finch" <robfinch@robf...>
To: <fpga-cpu@fpga...>
Sent: Saturday, April 02, 2005 8:47 PM
Subject: [fpga-cpu] Use for 2 bit opcode ? >
>
> Can anyone think of a use for a two bit opcode ?
>
> It all started when I decided to use a 42 bit code. Three opcodes are
> packed into 128 bits, but that leaves 2 bits left over, so what can I
> do with them ?
Lisp machines had tag bits, perhaps you can use them for something similar.
Leon
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Use for 2 bit opcode ? - woodelf - Apr 2 16:32:00 2005
Leon Heller wrote:
>>Can anyone think of a use for a two bit opcode ?
>>
>>It all started when I decided to use a 42 bit code. Three opcodes are
>>packed into 128 bits, but that leaves 2 bits left over, so what can I
>>do with them ?
>>
>>
>
>Lisp machines had tag bits, perhaps you can use them for something similar.
>
>Leon >
But this is opcodes ... My guess could be a return instruction ... 0 no
return 1 return after instruction #1
2 return after instruction #2 3 return after instruction #3
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>>Can anyone think of a use for a two bit opcode ?
>>
>>It all started when I decided to use a 42 bit code. Three opcodes are
>>packed into 128 bits, but that leaves 2 bits left over, so what can I
>>do with them ?
>>
>>
>
>Lisp machines had tag bits, perhaps you can use them for something similar.
>
>Leon >
But this is opcodes ... My guess could be a return instruction ... 0 no
return 1 return after instruction #1
2 return after instruction #2 3 return after instruction #3
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Re: Use for 2 bit opcode ? - Kolja Sulimma - Apr 2 17:17:00 2005
Rob Finch wrote:
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, but that leaves 2 bits left over, so what can I
>do with them ? Some ideas:
-Two flags for conditional execution
(Bit 0 says execute instruction 0 and 1 in this word only if the last
comparison was successfull, the other bit says the same for the
remaining instruction)
-large immediates
If the bit 0 is set the opcode for instruction 2 in the word becomes a
32-bit immediate for the first operand of instruction 0
-flag to switch virtual register files
You have two sets of register files. One set supplies source operands
and the other one is only used as destination operands.
Whenever the bit is set role of the two are switched. This guarantees
that all instructions with the same bit value can be executed in any
order or in parallel. This is a nice way to have an abstract ISA for
VLIW where you do not know the number of instruction units in advance.
- flag whether there is a branch delay slot
Have fun,
Kolja Sulimma
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>Can anyone think of a use for a two bit opcode ?
>
>It all started when I decided to use a 42 bit code. Three opcodes are
>packed into 128 bits, but that leaves 2 bits left over, so what can I
>do with them ? Some ideas:
-Two flags for conditional execution
(Bit 0 says execute instruction 0 and 1 in this word only if the last
comparison was successfull, the other bit says the same for the
remaining instruction)
-large immediates
If the bit 0 is set the opcode for instruction 2 in the word becomes a
32-bit immediate for the first operand of instruction 0
-flag to switch virtual register files
You have two sets of register files. One set supplies source operands
and the other one is only used as destination operands.
Whenever the bit is set role of the two are switched. This guarantees
that all instructions with the same bit value can be executed in any
order or in parallel. This is a nice way to have an abstract ISA for
VLIW where you do not know the number of instruction units in advance.
- flag whether there is a branch delay slot
Have fun,
Kolja Sulimma
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Use for 2 bit opcode ? - Rob Finch - Apr 2 18:30:00 2005
> -large immediates
> If the bit 0 is set the opcode for instruction 2 in the word becomes
a
> 32-bit immediate for the first operand of instruction 0 I like the large immediate idea. If I flag a whole opcode field as an
immediate, then I can squeeze 64 bit immediates into only two opcodes. > Have fun, Something I ran into today: why aren't branch displacements a
combination of both relative and absolute addressing ? The high order
bits of the displacement could be used as a relative offset to a block
of instructions, while the low order bits are used as an absolute
index. I'm thinking it would be handy to get rid of pc displacement
adder bits. It might be useful when the size of the design is
important. It would speed up the displacement adder as well. The low
order bits could just be passed directly through to the pc. With a
typical sixteen bit displacement, the low order twelve bits could be
passed along verbatium as a page index, while the high order four bits
select a block -8 to +7 blocks away.
______________________________
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Re: Re: Use for 2 bit opcode ? - Ben Franchuk - Apr 2 19:03:00 2005
Rob Finch wrote:
> Something I ran into today: why aren't branch displacements a
> combination of both relative and absolute addressing ? The high order
> bits of the displacement could be used as a relative offset to a block
> of instructions, while the low order bits are used as an absolute
> index. I'm thinking it would be handy to get rid of pc displacement
> adder bits. It might be useful when the size of the design is
> important. It would speed up the displacement adder as well. The low
> order bits could just be passed directly through to the pc. With a
> typical sixteen bit displacement, the low order twelve bits could be
> passed along verbatium as a page index, while the high order four bits
> select a block -8 to +7 blocks away.
>
Nice idea, just remember your code will relocate to 4k boundrys.
Ben alias woodelf
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> combination of both relative and absolute addressing ? The high order
> bits of the displacement could be used as a relative offset to a block
> of instructions, while the low order bits are used as an absolute
> index. I'm thinking it would be handy to get rid of pc displacement
> adder bits. It might be useful when the size of the design is
> important. It would speed up the displacement adder as well. The low
> order bits could just be passed directly through to the pc. With a
> typical sixteen bit displacement, the low order twelve bits could be
> passed along verbatium as a page index, while the high order four bits
> select a block -8 to +7 blocks away.
>
Nice idea, just remember your code will relocate to 4k boundrys.
Ben alias woodelf
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Chess Computer - John Kent - Apr 3 3:52:00 2005
Has there been any work done on FPGA Chess computers ?
I thought building an FPGA machine that generated a ply tree
would be pretty easy to do. The trick may be in working out
the best position analysis and evaluation strategy.
I remember many years ago seeing a hardwired chess computer,
in the newspaper. I'm not sure if if used FPGAs or not.
Did Deep Blue use FPGAs ?
John.
--
http://members.optushome.com.au/jekent
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I thought building an FPGA machine that generated a ply tree
would be pretty easy to do. The trick may be in working out
the best position analysis and evaluation strategy.
I remember many years ago seeing a hardwired chess computer,
in the newspaper. I'm not sure if if used FPGAs or not.
Did Deep Blue use FPGAs ?
John.
--
http://members.optushome.com.au/jekent
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Chess Computer - Kolja Sulimma - Apr 3 4:05:00 2005
John Kent wrote:
>Has there been any work done on FPGA Chess computers ? >
Yes.
http://www.hydrachess.com/
>Did Deep Blue use FPGAs ? No, ASICs
Kolja Sulimma
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>Has there been any work done on FPGA Chess computers ? >
Yes.
http://www.hydrachess.com/
>Did Deep Blue use FPGAs ? No, ASICs
Kolja Sulimma
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Chess Computer - John Kent - Apr 4 5:02:00 2005
Hi Kolja
Looks interesting.
One of the first projects I was interested in when I bought my 6800 D2 kit
back in the late 70s was converting Sargon from the Z80 to the 6800.
Dan and Kathe Spracklen released a book with the source code called
"Sargon: a Computer Chess Program"
http://www.answers.com/topic/sargon-chess
At the time we were using a 300baud Kansas City Standard tape loader.
We got so far coding it that my brother thought he'd throw away the source
and patch the binary ... BIG mistake !. He/we never did finish the project.
We got the game to make an opening move on the memory mapped VDU,
then BLAT, the opposition move scambled it's piece on the display.
Not good :-)
The Byte Book of Pascal had a chess program in it (am I showing my age?)
which was a tinsy bit to big for my 8 bit machine and the Lucidata Pcode
Pascal
compiler at the time.
I guess these days you have gnu chess, although I'd hate to try and
implement
that in hardware.
Anyway I have the Sargon source code book somewhere. I'm not sure if it is
possible to microcode a move generator that will go through all possible
movements
of a chess piece. Each move could be stored in a 12 x 12 nybble array
(8 x 8 with a 2 nybble perimeter to test for out of bounds moves).
I think that was how Sargon was implemented.
Empty, Pawn, Rook, Knight, Bishop, Queen, King and Boundary could be
code in 3 bits
and one bit for the side (white / black)
With 256K bytes of RAM, that would allow 3640 moves to be stored.
My guess is that hydrachess is a parallel archictecture which just farms
off more
moves in each of the processors.
Evaluation of a position would take into account which pieces were being
attacked
which pieces were attacking, how many peices were defending other peices and
how many squares the peices controlled. Also if you where in check !
The end game probably demands another strategy ... how to get the
opponent in check mate. Maybe that comes out in the wash, by virtue of
the squares being controlled.
Just a few thoughts to fill up peoples mailboxes :-)
John.
Kolja Sulimma wrote:
>John Kent wrote: >
>>Has there been any work done on FPGA Chess computers ?
>>
>>
>>
>>
>>
>Yes.
>http://www.hydrachess.com/ >
>>Did Deep Blue use FPGAs ?
>>
>>
>>
>>
>No, ASICs
>
>Kolja Sulimma --
http://members.optushome.com.au/jekent
[Non-text portions of this message have been removed]
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Looks interesting.
One of the first projects I was interested in when I bought my 6800 D2 kit
back in the late 70s was converting Sargon from the Z80 to the 6800.
Dan and Kathe Spracklen released a book with the source code called
"Sargon: a Computer Chess Program"
http://www.answers.com/topic/sargon-chess
At the time we were using a 300baud Kansas City Standard tape loader.
We got so far coding it that my brother thought he'd throw away the source
and patch the binary ... BIG mistake !. He/we never did finish the project.
We got the game to make an opening move on the memory mapped VDU,
then BLAT, the opposition move scambled it's piece on the display.
Not good :-)
The Byte Book of Pascal had a chess program in it (am I showing my age?)
which was a tinsy bit to big for my 8 bit machine and the Lucidata Pcode
Pascal
compiler at the time.
I guess these days you have gnu chess, although I'd hate to try and
implement
that in hardware.
Anyway I have the Sargon source code book somewhere. I'm not sure if it is
possible to microcode a move generator that will go through all possible
movements
of a chess piece. Each move could be stored in a 12 x 12 nybble array
(8 x 8 with a 2 nybble perimeter to test for out of bounds moves).
I think that was how Sargon was implemented.
Empty, Pawn, Rook, Knight, Bishop, Queen, King and Boundary could be
code in 3 bits
and one bit for the side (white / black)
With 256K bytes of RAM, that would allow 3640 moves to be stored.
My guess is that hydrachess is a parallel archictecture which just farms
off more
moves in each of the processors.
Evaluation of a position would take into account which pieces were being
attacked
which pieces were attacking, how many peices were defending other peices and
how many squares the peices controlled. Also if you where in check !
The end game probably demands another strategy ... how to get the
opponent in check mate. Maybe that comes out in the wash, by virtue of
the squares being controlled.
Just a few thoughts to fill up peoples mailboxes :-)
John.
Kolja Sulimma wrote:
>John Kent wrote: >
>>Has there been any work done on FPGA Chess computers ?
>>
>>
>>
>>
>>
>Yes.
>http://www.hydrachess.com/ >
>>Did Deep Blue use FPGAs ?
>>
>>
>>
>>
>No, ASICs
>
>Kolja Sulimma --
http://members.optushome.com.au/jekent
[Non-text portions of this message have been removed]
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Chess Computer - Kolja Sulimma - Apr 4 5:09:00 2005
There was a paper about Hydra in last years FPL conference. I think they
had an architecture with a processing element per square.
But apparently a lot of their know-how is an efficient partitioning
between smart high level algorithms running in software and parallel
brute force search running in dozens of FPGAs.
Kolja
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
had an architecture with a processing element per square.
But apparently a lot of their know-how is an efficient partitioning
between smart high level algorithms running in software and parallel
brute force search running in dozens of FPGAs.
Kolja
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Chess Computer - Leon Heller - Apr 4 5:20:00 2005
----- Original Message -----
From: "John Kent" <jekent@jeke...>
To: <fpga-cpu@fpga...>
Sent: Monday, April 04, 2005 10:02 AM
Subject: Re: [fpga-cpu] Chess Computer >
> Hi Kolja
>
> Looks interesting.
>
> One of the first projects I was interested in when I bought my 6800 D2
> kit
> back in the late 70s was converting Sargon from the Z80 to the 6800.
> Dan and Kathe Spracklen released a book with the source code called
> "Sargon: a Computer Chess Program"
>
> http://www.answers.com/topic/sargon-chess
>
> At the time we were using a 300baud Kansas City Standard tape loader.
> We got so far coding it that my brother thought he'd throw away the source
> and patch the binary ... BIG mistake !. He/we never did finish the
> project.
> We got the game to make an opening move on the memory mapped VDU,
> then BLAT, the opposition move scambled it's piece on the display.
> Not good :-)
My first 'computer' was the D2 kit. It cost me 209 GBP IIRC, quite a lot of
money in those days. It came with 128 bytes of user RAM, I added another
chip and had all of 256 bytes available. I hand-assembled the little
programs I wrote.
Leon
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
From: "John Kent" <jekent@jeke...>
To: <fpga-cpu@fpga...>
Sent: Monday, April 04, 2005 10:02 AM
Subject: Re: [fpga-cpu] Chess Computer >
> Hi Kolja
>
> Looks interesting.
>
> One of the first projects I was interested in when I bought my 6800 D2
> kit
> back in the late 70s was converting Sargon from the Z80 to the 6800.
> Dan and Kathe Spracklen released a book with the source code called
> "Sargon: a Computer Chess Program"
>
> http://www.answers.com/topic/sargon-chess
>
> At the time we were using a 300baud Kansas City Standard tape loader.
> We got so far coding it that my brother thought he'd throw away the source
> and patch the binary ... BIG mistake !. He/we never did finish the
> project.
> We got the game to make an opening move on the memory mapped VDU,
> then BLAT, the opposition move scambled it's piece on the display.
> Not good :-)
My first 'computer' was the D2 kit. It cost me 209 GBP IIRC, quite a lot of
money in those days. It came with 128 bytes of user RAM, I added another
chip and had all of 256 bytes available. I hand-assembled the little
programs I wrote.
Leon
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Chess Computer - rtstofer - Apr 4 10:21:00 2005
John,
I have source for Digital Research's demo chess program written in
PL/I if you have a need.
Richard
--- In fpga-cpu@fpga..., "Leon Heller" <leon.heller@d...>
wrote:
> ----- Original Message -----
> From: "John Kent" <jekent@o...>
> To: <fpga-cpu@fpga...>
> Sent: Monday, April 04, 2005 10:02 AM
> Subject: Re: [fpga-cpu] Chess Computer > >
> > Hi Kolja
> >
> > Looks interesting.
> >
> > One of the first projects I was interested in when I bought my
6800 D2
> > kit
> > back in the late 70s was converting Sargon from the Z80 to the
6800.
> > Dan and Kathe Spracklen released a book with the source code
called
> > "Sargon: a Computer Chess Program"
> >
> > http://www.answers.com/topic/sargon-chess
> >
> > At the time we were using a 300baud Kansas City Standard tape
loader.
> > We got so far coding it that my brother thought he'd throw away
the source
> > and patch the binary ... BIG mistake !. He/we never did finish
the
> > project.
> > We got the game to make an opening move on the memory mapped VDU,
> > then BLAT, the opposition move scambled it's piece on the
display.
> > Not good :-)
>
> My first 'computer' was the D2 kit. It cost me 209 GBP IIRC, quite
a lot of
> money in those days. It came with 128 bytes of user RAM, I added
another
> chip and had all of 256 bytes available. I hand-assembled the
little
> programs I wrote.
>
> Leon
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
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Re: Re: Use for 2 bit opcode ? - Tomasz Sztejka - Apr 4 10:47:00 2005
--- Rob Finch <robfinch@robf...> wrote:
>
(...)
> Something I ran into today: why aren't branch
> displacements a
> combination of both relative and absolute addressing ?
> The high order
> bits of the displacement could be used as a relative
> offset to a block
> of instructions, while the low order bits are used as an
> absolute
> index.
(...)
Because it joins all disadvantages of relative addressing
and absolute. You will need an adder anyway to add most
significant bits. And you will get PAGES (programmers hate
PAGED addressing) within which each subroutine will have to
fit. It complicates linker and compiler alot.
Can you do long branches then by combinig sequence of
short relative jumps? If pages won't overlap the answer is
no. But it does not matter when you have absolute/long
branch opcode in your ISA.
In my opinion, if displacement adder matters to size of
desing use absolute addressing with separate page latch
register for bits which does not fit in opcode. Be prepared
that the guy who will write compile will hate you. If you
find that ease of programming is more important use full
relative displacement.
Tomasz Sztejka.
Send instant messages to your online friends http://uk.messenger.yahoo.com
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Re: Re: Use for 2 bit opcode ? - Ben Franchuk - Apr 4 22:12:00 2005
Rob Finch wrote:
> Maybe I should mention this is for my SuperUltraGeeWhizzExtraNew
> desktop cpu design, it's not an embedded system design. The cpu is
> using virtual memory so the need for relocatble code is not so much.
Hey that sounds like the name I want to call my table top cpu design.
Is your Instruction Set Documented on your site yet?
> The problem with branches stems from the fact I'm using 42 bit
> opcodes packed into 128 bits. There isn't a way to calculate a
> constant relative displacement for completely relocatable code. (eg
> relocatable by instruction slots - the pc increments 0,1,2,0,1,2,...)
> Relocatability has to be restricted to at least 16 byte (128 bit)
> boundaries. Since there is a restriction anyway, I figure might as
> well make it a real PITA and conserve some hardware / improve
> performance. (If you're going to create a PITA, do a good job of
> it :).
That is true removing long branches will save some time.
Note if you sort you data space you don't need to use large
data offesets. Offhand you really only need about max_word_size **.5
for offsets.
> What's wrong with pages ? Programmers love pages. They hate
> segmentation and bank switching.
Well I consider most programs to be about 3 sizes.
<= 64KB >64KB and bloated stuff.
> Each subroutine does not have to fit
> within a page and it does not have to begin on a page boundary. The
> subroutines can be coded anywhere and be any size. The only
> restriction comes into play if one wants relocatable code. Then the
> code can only be relocated according to the number of bits used for
> absolute addressing. I'm choosing the memory management page size as
> the size to use for the absolute portion. Being able to relocate
> things based on a page versus a byte boundary isn't that much of an
> issue.
> Sure you can. There's no dependency between instructions.
> The ISA does have absolute jumps and calls as well.
I think absolute calls are only need for system traps
and jumps for interupt stuff.
> There are other things that can benefit from using a combo approach.
> For instance the branch target may be being calculated during the ID
> or even IF stage and the target calculation needs to be as fast as
> possible. Trimming a few bits off the adder doesn't hurt. The branch
> target is also used to index into a target buffer. Not having to go
> through an adder first helps.
>
Ben alias woodelf.
PS. Since I am only doing a 16 bit CPU I need a bigger name than
your 128? bit CPU --- any good ideas.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Maybe I should mention this is for my SuperUltraGeeWhizzExtraNew
> desktop cpu design, it's not an embedded system design. The cpu is
> using virtual memory so the need for relocatble code is not so much.
Hey that sounds like the name I want to call my table top cpu design.
Is your Instruction Set Documented on your site yet?
> The problem with branches stems from the fact I'm using 42 bit
> opcodes packed into 128 bits. There isn't a way to calculate a
> constant relative displacement for completely relocatable code. (eg
> relocatable by instruction slots - the pc increments 0,1,2,0,1,2,...)
> Relocatability has to be restricted to at least 16 byte (128 bit)
> boundaries. Since there is a restriction anyway, I figure might as
> well make it a real PITA and conserve some hardware / improve
> performance. (If you're going to create a PITA, do a good job of
> it :).
That is true removing long branches will save some time.
Note if you sort you data space you don't need to use large
data offesets. Offhand you really only need about max_word_size **.5
for offsets.
> What's wrong with pages ? Programmers love pages. They hate
> segmentation and bank switching.
Well I consider most programs to be about 3 sizes.
<= 64KB >64KB and bloated stuff.
> Each subroutine does not have to fit
> within a page and it does not have to begin on a page boundary. The
> subroutines can be coded anywhere and be any size. The only
> restriction comes into play if one wants relocatable code. Then the
> code can only be relocated according to the number of bits used for
> absolute addressing. I'm choosing the memory management page size as
> the size to use for the absolute portion. Being able to relocate
> things based on a page versus a byte boundary isn't that much of an
> issue.
> Sure you can. There's no dependency between instructions.
> The ISA does have absolute jumps and calls as well.
I think absolute calls are only need for system traps
and jumps for interupt stuff.
> There are other things that can benefit from using a combo approach.
> For instance the branch target may be being calculated during the ID
> or even IF stage and the target calculation needs to be as fast as
> possible. Trimming a few bits off the adder doesn't hurt. The branch
> target is also used to index into a target buffer. Not having to go
> through an adder first helps.
>
Ben alias woodelf.
PS. Since I am only doing a 16 bit CPU I need a bigger name than
your 128? bit CPU --- any good ideas.
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