Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | sdf simulations
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
sdf simulations - Rahul Vishal - Apr 21 22:56:00 2005
Hi everyone,
I am trying to do a post layout simulation. One that is done after the PnR
is over. I have got the Vhdl netlist and also the sdf file. But the
NClaunch gives me all kinds of warnings like : Component Instance not
fully bound and so on. Is there any place I can look for a solution? Can
anybody help me ???
Bye
Rahul -----------------------------------------
Stay ahead of the information curve.
Receive EDA news and jobs on your desktop daily.
Subscribe today to the EDA CafeNews newsletter.
[ http://www10.edacafe.com/nl/newsletter_subscribe.php ]
It's informative and essential.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )