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Discussion Groups | FPGA-CPU | Parallel Port Programming Of Spartan IIE
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Parallel Port Programming Of Spartan IIE - rtstofer - Jun 7 9:05:00 2005
Has anybody seen an app note that shows direct programming of a
Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
intermediate device such as a CPLD?
I'm building another version of a logic analyzer with a 300k Spartan
IIE and using the PC parallel port in EPP mode (bidirectional 8 bit
with 6 control lines) rather than Centronics mode. It would be no
real effort to have the application code download the configuration.
I realize I could use JTAG with or without a platform flash and have a
better solution but I am trying to build this thing with exactly 1
chip (plus an oscillator) for no particularly good reason.
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
intermediate device such as a CPLD?
I'm building another version of a logic analyzer with a 300k Spartan
IIE and using the PC parallel port in EPP mode (bidirectional 8 bit
with 6 control lines) rather than Centronics mode. It would be no
real effort to have the application code download the configuration.
I realize I could use JTAG with or without a platform flash and have a
better solution but I am trying to build this thing with exactly 1
chip (plus an oscillator) for no particularly good reason.
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Parallel Port Programming Of Spartan IIE - Peter C. Wallace - Jun 7 9:49:00 2005
On Tue, 7 Jun 2005, rtstofer wrote:
> Has anybody seen an app note that shows direct programming of a
> Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
> intermediate device such as a CPLD?
>
> I'm building another version of a logic analyzer with a 300k Spartan
> IIE and using the PC parallel port in EPP mode (bidirectional 8 bit
> with 6 control lines) rather than Centronics mode. It would be no
> real effort to have the application code download the configuration.
>
> I realize I could use JTAG with or without a platform flash and have a
> better solution but I am trying to build this thing with exactly 1
> chip (plus an oscillator) for no particularly good reason.
Should be trivial in byte parallel configuration mode. Connect some free
parallel port I/O bit to /PROGRAM (if you need to be able to re-program it),
PSTB to CCLK, and the PDATA bits to XILINX Config bits 0..7 (backwards: PDATA0
to XL7, PDATA1 to XL6 etc,etc)
You would need series resistors to protect the Spartan from 5V parallel port
outputs.
Though it goes against your 1 chip rule, I would add a RC/Schmitt trigger
on the PSTB used for configuration clock, since it may not be very clean on
the far end of a long parallel port cable, and the CCLK input is fast enough
to see any glitches... > To post a message, send it to: fpga-cpu@fpga...
> To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@fpga...
> Yahoo! Groups Links >
Peter Wallace
Mesa Electronics
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Has anybody seen an app note that shows direct programming of a
> Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
> intermediate device such as a CPLD?
>
> I'm building another version of a logic analyzer with a 300k Spartan
> IIE and using the PC parallel port in EPP mode (bidirectional 8 bit
> with 6 control lines) rather than Centronics mode. It would be no
> real effort to have the application code download the configuration.
>
> I realize I could use JTAG with or without a platform flash and have a
> better solution but I am trying to build this thing with exactly 1
> chip (plus an oscillator) for no particularly good reason.
Should be trivial in byte parallel configuration mode. Connect some free
parallel port I/O bit to /PROGRAM (if you need to be able to re-program it),
PSTB to CCLK, and the PDATA bits to XILINX Config bits 0..7 (backwards: PDATA0
to XL7, PDATA1 to XL6 etc,etc)
You would need series resistors to protect the Spartan from 5V parallel port
outputs.
Though it goes against your 1 chip rule, I would add a RC/Schmitt trigger
on the PSTB used for configuration clock, since it may not be very clean on
the far end of a long parallel port cable, and the CCLK input is fast enough
to see any glitches... > To post a message, send it to: fpga-cpu@fpga...
> To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@fpga...
> Yahoo! Groups Links >
Peter Wallace
Mesa Electronics
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Parallel Port Programming Of Spartan IIE - rtstofer - Jun 7 11:36:00 2005
--- In fpga-cpu@fpga..., "Peter C. Wallace" <pcw@m...> wrote:
> On Tue, 7 Jun 2005, rtstofer wrote:
>
> > Has anybody seen an app note that shows direct programming of a
> > Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
> > intermediate device such as a CPLD?
> >
> > I'm building another version of a logic analyzer with a 300k Spartan
> > IIE and using the PC parallel port in EPP mode (bidirectional 8 bit
> > with 6 control lines) rather than Centronics mode. It would be no
> > real effort to have the application code download the configuration.
> >
> > I realize I could use JTAG with or without a platform flash and have a
> > better solution but I am trying to build this thing with exactly 1
> > chip (plus an oscillator) for no particularly good reason.
> > Should be trivial in byte parallel configuration mode. Connect some
free
> parallel port I/O bit to /PROGRAM (if you need to be able to
re-program it),
> PSTB to CCLK, and the PDATA bits to XILINX Config bits 0..7
(backwards: PDATA0
> to XL7, PDATA1 to XL6 etc,etc)
>
> You would need series resistors to protect the Spartan from 5V
parallel port
> outputs.
>
> Though it goes against your 1 chip rule, I would add a RC/Schmitt
trigger
> on the PSTB used for configuration clock, since it may not be very
clean on
> the far end of a long parallel port cable, and the CCLK input is
fast enough
> to see any glitches...
>
> >
> >
> >
> >
> > To post a message, send it to: fpga-cpu@fpga...
> > To unsubscribe, send a blank message to:
fpga-cpu-unsubscribe@fpga...
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
>
> Peter Wallace
> Mesa Electronics
I have studied the data sheet and have come to the same conclusion
but... I really wanted to see it written down somewhere. The chip is
about $40 and the board to put it on is about $60 (for qty 3 but I'm
only building 1) so if I get it wrong, my minimum loss is $60 (plus
time). I would like to avoid this, if possible, and I don't have a
stellar record for perfect design.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> On Tue, 7 Jun 2005, rtstofer wrote:
>
> > Has anybody seen an app note that shows direct programming of a
> > Spartan IIE from a PC parallel port without using iMPACT, JTAG or an
> > intermediate device such as a CPLD?
> >
> > I'm building another version of a logic analyzer with a 300k Spartan
> > IIE and using the PC parallel port in EPP mode (bidirectional 8 bit
> > with 6 control lines) rather than Centronics mode. It would be no
> > real effort to have the application code download the configuration.
> >
> > I realize I could use JTAG with or without a platform flash and have a
> > better solution but I am trying to build this thing with exactly 1
> > chip (plus an oscillator) for no particularly good reason.
> > Should be trivial in byte parallel configuration mode. Connect some
free
> parallel port I/O bit to /PROGRAM (if you need to be able to
re-program it),
> PSTB to CCLK, and the PDATA bits to XILINX Config bits 0..7
(backwards: PDATA0
> to XL7, PDATA1 to XL6 etc,etc)
>
> You would need series resistors to protect the Spartan from 5V
parallel port
> outputs.
>
> Though it goes against your 1 chip rule, I would add a RC/Schmitt
trigger
> on the PSTB used for configuration clock, since it may not be very
clean on
> the far end of a long parallel port cable, and the CCLK input is
fast enough
> to see any glitches...
>
> >
> >
> >
> >
> > To post a message, send it to: fpga-cpu@fpga...
> > To unsubscribe, send a blank message to:
fpga-cpu-unsubscribe@fpga...
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
>
> Peter Wallace
> Mesa Electronics
I have studied the data sheet and have come to the same conclusion
but... I really wanted to see it written down somewhere. The chip is
about $40 and the board to put it on is about $60 (for qty 3 but I'm
only building 1) so if I get it wrong, my minimum loss is $60 (plus
time). I would like to avoid this, if possible, and I don't have a
stellar record for perfect design.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )