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Discussion Groups | FPGA-CPU | Pentium timing diagrams?
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Pentium timing diagrams? - NeilS - Jun 28 10:06:00 2005
Hello everyone,
Just wondering if anyone has seen or has access to the timing diagrams
for the transactions between a 'classic' Pentium (3.3V core, 75 thru
200MHz) and its chipset? I'm interested in having a go at implementing
minimalist support in a CPLD, just to allow access to ROM and some I/O
for now and turn it into a microcontroller of sorts.
Would appreciate any help and I have already checked the Intel
developer site.
Thanks, Neil
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Just wondering if anyone has seen or has access to the timing diagrams
for the transactions between a 'classic' Pentium (3.3V core, 75 thru
200MHz) and its chipset? I'm interested in having a go at implementing
minimalist support in a CPLD, just to allow access to ROM and some I/O
for now and turn it into a microcontroller of sorts.
Would appreciate any help and I have already checked the Intel
developer site.
Thanks, Neil
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )