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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Optimal states per bit - Veronica Merryfield - Jul 22 2:26:00 2005
I wonder if anyone can give me some pointers on this.
Way back when I was at university, I can remember a tutorial on deriving the
optimal number of states per bit for a microprocessor based system using
information theory as the starting point. It finished with 2.71828.
He then went on to explain that whilst ternary would be better, magnetic
media in the early days would not have worked hence going for binary.
I would really like to find the background to and the actual derivation. My
notes are long gone.
Thanks in advance
Veronica
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Way back when I was at university, I can remember a tutorial on deriving the
optimal number of states per bit for a microprocessor based system using
information theory as the starting point. It finished with 2.71828.
He then went on to explain that whilst ternary would be better, magnetic
media in the early days would not have worked hence going for binary.
I would really like to find the background to and the actual derivation. My
notes are long gone.
Thanks in advance
Veronica
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Optimal states per bit - rtstofer - Jul 22 9:43:00 2005
--- In fpga-cpu@fpga..., Veronica Merryfield
<veronica.merryfield@t...> wrote:
> I wonder if anyone can give me some pointers on this.
>
> Way back when I was at university, I can remember a tutorial on
deriving the
> optimal number of states per bit for a microprocessor based system
using
> information theory as the starting point. It finished with 2.71828.
>
> He then went on to explain that whilst ternary would be better,
magnetic
> media in the early days would not have worked hence going for binary.
>
> I would really like to find the background to and the actual
derivation. My
> notes are long gone.
>
> Thanks in advance
>
> Veronica
I would imagine there are very few people who encountered this
particular derivation and even fewer that remember. It goes WAY back!
I think I ran into it in undergrad, some time prior to '73.
As I recall, it was a cost model: a cost for a resistor, a cost for a
diode (yes, we're talking discrete logic) and a much higher cost for a
transistor. The costs were tabulated versus states per bit and out
came the idea that logic should be base 'e'. I don't recall it being
at all related to information theory but I suppose the same result
could be achieved from different directions.
I'm sorry I can't lay my hands on the reference. I wouldn't be
surprised to find that I still have it but it didn't jump right off
the shelf.
Richard
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
<veronica.merryfield@t...> wrote:
> I wonder if anyone can give me some pointers on this.
>
> Way back when I was at university, I can remember a tutorial on
deriving the
> optimal number of states per bit for a microprocessor based system
using
> information theory as the starting point. It finished with 2.71828.
>
> He then went on to explain that whilst ternary would be better,
magnetic
> media in the early days would not have worked hence going for binary.
>
> I would really like to find the background to and the actual
derivation. My
> notes are long gone.
>
> Thanks in advance
>
> Veronica
I would imagine there are very few people who encountered this
particular derivation and even fewer that remember. It goes WAY back!
I think I ran into it in undergrad, some time prior to '73.
As I recall, it was a cost model: a cost for a resistor, a cost for a
diode (yes, we're talking discrete logic) and a much higher cost for a
transistor. The costs were tabulated versus states per bit and out
came the idea that logic should be base 'e'. I don't recall it being
at all related to information theory but I suppose the same result
could be achieved from different directions.
I'm sorry I can't lay my hands on the reference. I wouldn't be
surprised to find that I still have it but it didn't jump right off
the shelf.
Richard
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
RE: Re: Optimal states per bit - vero...@... - Jul 22 12:15:00 2005
Thanks for that Richard
>I would imagine there are very few people who encountered this
>particular derivation and even fewer that remember. It goes WAY back!
>I think I ran into it in undergrad, some time prior to '73.
It sure does go back a bit. I encountered this in '84/'85.
>As I recall, it was a cost model: a cost for a resistor, a cost for a
This one I remember
>came the idea that logic should be base 'e'. I don't recall it being
>at all related to information theory but I suppose the same result
>could be achieved from different directions.
Which is why I wanted to find this one as it is much rarer as far as I can
tell, and of interest to me now.
Veronica
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>I would imagine there are very few people who encountered this
>particular derivation and even fewer that remember. It goes WAY back!
>I think I ran into it in undergrad, some time prior to '73.
It sure does go back a bit. I encountered this in '84/'85.
>As I recall, it was a cost model: a cost for a resistor, a cost for a
This one I remember
>came the idea that logic should be base 'e'. I don't recall it being
>at all related to information theory but I suppose the same result
>could be achieved from different directions.
Which is why I wanted to find this one as it is much rarer as far as I can
tell, and of interest to me now.
Veronica
--------------------------------------------------------------------
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http://mail2web.com/ .
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Re: Re: Optimal states per bit - Jeff Brower - Jul 22 12:52:00 2005
Veronica-
> Thanks for that Richard
>
> >I would imagine there are very few people who encountered this
> >particular derivation and even fewer that remember. It goes WAY back!
> >I think I ran into it in undergrad, some time prior to '73.
> It sure does go back a bit. I encountered this in '84/'85.
>
> >As I recall, it was a cost model: a cost for a resistor, a cost for a
> This one I remember
>
> >came the idea that logic should be base 'e'. I don't recall it being
> >at all related to information theory but I suppose the same result
> >could be achieved from different directions.
> Which is why I wanted to find this one as it is much rarer as far as I can
> tell, and of interest to me now.
Resistors, diodes? That would be a dated cost model, right. This page attempts an
implementation-independent mathematical proof that base e is optimum for computing
machines:
http://www.americanscientist.org/template/AssetDetail/assetid/14405?&print=yes
"...if r is the radix and w is the width in digits, we want
to minimize rw while holding rw constant..."
-Jeff
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Thanks for that Richard
>
> >I would imagine there are very few people who encountered this
> >particular derivation and even fewer that remember. It goes WAY back!
> >I think I ran into it in undergrad, some time prior to '73.
> It sure does go back a bit. I encountered this in '84/'85.
>
> >As I recall, it was a cost model: a cost for a resistor, a cost for a
> This one I remember
>
> >came the idea that logic should be base 'e'. I don't recall it being
> >at all related to information theory but I suppose the same result
> >could be achieved from different directions.
> Which is why I wanted to find this one as it is much rarer as far as I can
> tell, and of interest to me now.
Resistors, diodes? That would be a dated cost model, right. This page attempts an
implementation-independent mathematical proof that base e is optimum for computing
machines:
http://www.americanscientist.org/template/AssetDetail/assetid/14405?&print=yes
"...if r is the radix and w is the width in digits, we want
to minimize rw while holding rw constant..."
-Jeff
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - woodelf - Jul 22 14:18:00 2005
Jeff Brower wrote:
> Resistors, diodes? That would be a dated cost model, right. This page attempts an
> implementation-independent mathematical proof that base e is optimum for computing
> machines:
>
> http://www.americanscientist.org/template/AssetDetail/assetid/14405?&print=yes
>
> "...if r is the radix and w is the width in digits, we want
> to minimize rw while holding rw constant..."
But right now we are still stuck with
binary memory and that limits any new computing
models.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Resistors, diodes? That would be a dated cost model, right. This page attempts an
> implementation-independent mathematical proof that base e is optimum for computing
> machines:
>
> http://www.americanscientist.org/template/AssetDetail/assetid/14405?&print=yes
>
> "...if r is the radix and w is the width in digits, we want
> to minimize rw while holding rw constant..."
But right now we are still stuck with
binary memory and that limits any new computing
models.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - Kolja Sulimma - Jul 22 14:54:00 2005
woodelf schrieb:
>Jeff Brower wrote: >
>>Resistors, diodes? That would be a dated cost model, right. This page attempts an
>>implementation-independent mathematical proof that base e is optimum for computing
>>machines:
>>
>> http://www.americanscientist.org/template/AssetDetail/assetid/14405?&print=yes
>>
>> "...if r is the radix and w is the width in digits, we want
>> to minimize rw while holding rw constant..."
>>
>>
>
>But right now we are still stuck with
>binary memory and that limits any new computing
>models. Also, those artikels are about number representation.
The cost for the arithmetik circuits to do anything useful with those
numbers are not taken into account.
As the table size for an one digit operation is r*r one could argue that
instead r*r*w should be minimized....
Kolja Sulimma
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>Jeff Brower wrote: >
>>Resistors, diodes? That would be a dated cost model, right. This page attempts an
>>implementation-independent mathematical proof that base e is optimum for computing
>>machines:
>>
>> http://www.americanscientist.org/template/AssetDetail/assetid/14405?&print=yes
>>
>> "...if r is the radix and w is the width in digits, we want
>> to minimize rw while holding rw constant..."
>>
>>
>
>But right now we are still stuck with
>binary memory and that limits any new computing
>models. Also, those artikels are about number representation.
The cost for the arithmetik circuits to do anything useful with those
numbers are not taken into account.
As the table size for an one digit operation is r*r one could argue that
instead r*r*w should be minimized....
Kolja Sulimma
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Optimal states per bit - rtstofer - Jul 22 15:00:00 2005
--- In fpga-cpu@fpga..., woodelf <bfranchuk@j...> wrote:
> Jeff Brower wrote:
>
> > Resistors, diodes? That would be a dated cost model, right.
This page attempts an
> > implementation-independent mathematical proof that base e is
optimum for computing
> > machines:
> >
> >
http://www.americanscientist.org/template/AssetDetail/assetid/14405?
&print=yes
> >
> > "...if r is the radix and w is the width in digits, we want
> > to minimize rw while holding rw constant..."
>
> But right now we are still stuck with
> binary memory and that limits any new computing
> models.
Yes, at the moment! I remember reading about this idea many years
ago and, at the time, I thought 'so what'? I couldn't represent a
trit in hardware so it wasn't particularly useful to know that it
would provide a reduced cost.
It just seemed strange for someone to bring up this concept after so
many years. Even stranger that I actually remembered - sometimes I
can't even remember why I went to the garage.
But, finding a web page? Incredible!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Jeff Brower wrote:
>
> > Resistors, diodes? That would be a dated cost model, right.
This page attempts an
> > implementation-independent mathematical proof that base e is
optimum for computing
> > machines:
> >
> >
http://www.americanscientist.org/template/AssetDetail/assetid/14405?
&print=yes
> >
> > "...if r is the radix and w is the width in digits, we want
> > to minimize rw while holding rw constant..."
>
> But right now we are still stuck with
> binary memory and that limits any new computing
> models.
Yes, at the moment! I remember reading about this idea many years
ago and, at the time, I thought 'so what'? I couldn't represent a
trit in hardware so it wasn't particularly useful to know that it
would provide a reduced cost.
It just seemed strange for someone to bring up this concept after so
many years. Even stranger that I actually remembered - sometimes I
can't even remember why I went to the garage.
But, finding a web page? Incredible!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - woodelf - Jul 22 16:30:00 2005
rtstofer wrote:
> Yes, at the moment! I remember reading about this idea many years
> ago and, at the time, I thought 'so what'? I couldn't represent a
> trit in hardware so it wasn't particularly useful to know that it
> would provide a reduced cost.
>
> It just seemed strange for someone to bring up this concept after so
> many years. Even stranger that I actually remembered - sometimes I
> can't even remember why I went to the garage.
>
> But, finding a web page? Incredible! But just how does one do the math and what about trinary logic
as compared to binary logic? I have liked the idea of trinary
logic but have never seen much more on the subject.
Ben alias woodelf
Have CPLD , will travel. :)
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Yes, at the moment! I remember reading about this idea many years
> ago and, at the time, I thought 'so what'? I couldn't represent a
> trit in hardware so it wasn't particularly useful to know that it
> would provide a reduced cost.
>
> It just seemed strange for someone to bring up this concept after so
> many years. Even stranger that I actually remembered - sometimes I
> can't even remember why I went to the garage.
>
> But, finding a web page? Incredible! But just how does one do the math and what about trinary logic
as compared to binary logic? I have liked the idea of trinary
logic but have never seen much more on the subject.
Ben alias woodelf
Have CPLD , will travel. :)
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Optimal states per bit - rtstofer - Jul 22 17:23:00 2005
--- In fpga-cpu@fpga..., woodelf <bfranchuk@j...> wrote:
> rtstofer wrote:
>
> > Yes, at the moment! I remember reading about this idea many
years
> > ago and, at the time, I thought 'so what'? I couldn't represent
a
> > trit in hardware so it wasn't particularly useful to know that
it
> > would provide a reduced cost.
> >
> > It just seemed strange for someone to bring up this concept
after so
> > many years. Even stranger that I actually remembered -
sometimes I
> > can't even remember why I went to the garage.
> >
> > But, finding a web page? Incredible!
> >
>
> But just how does one do the math and what about trinary logic
> as compared to binary logic? I have liked the idea of trinary
> logic but have never seen much more on the subject.
> Ben alias woodelf
> Have CPLD , will travel. :)
Well, in the form 'balanced ternary' the math is described in "The
Art Of Computer Programming - Vol. 2 Seminumerical Algorithms" by
Knuth, pg 174 of my 1969 edition.
BTW, the storage elements might be described as 'flip-flap-flops'.
Really! See page 175
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> rtstofer wrote:
>
> > Yes, at the moment! I remember reading about this idea many
years
> > ago and, at the time, I thought 'so what'? I couldn't represent
a
> > trit in hardware so it wasn't particularly useful to know that
it
> > would provide a reduced cost.
> >
> > It just seemed strange for someone to bring up this concept
after so
> > many years. Even stranger that I actually remembered -
sometimes I
> > can't even remember why I went to the garage.
> >
> > But, finding a web page? Incredible!
> >
>
> But just how does one do the math and what about trinary logic
> as compared to binary logic? I have liked the idea of trinary
> logic but have never seen much more on the subject.
> Ben alias woodelf
> Have CPLD , will travel. :)
Well, in the form 'balanced ternary' the math is described in "The
Art Of Computer Programming - Vol. 2 Seminumerical Algorithms" by
Knuth, pg 174 of my 1969 edition.
BTW, the storage elements might be described as 'flip-flap-flops'.
Really! See page 175
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - woodelf - Jul 22 18:23:00 2005
rtstofer wrote:
> Well, in the form 'balanced ternary' the math is described in "The
> Art Of Computer Programming - Vol. 2 Seminumerical Algorithms" by
> Knuth, pg 174 of my 1969 edition.
If I had the book, would I need to ask!
> BTW, the storage elements might be described as 'flip-flap-flops'.
> Really! See page 175
Better keep the books, since what I have seen for in Computer Science
is just RISC computer designs -- YUCK.
I think the only reason RISC machines made a impact is Efective Address
Calculations are fast on a RISC and all the modern addressing modes
use a lot of EFA addition.
Ben
PS.I like 1's compliemnt math but it don't handle multi-presison
operations well and that is needed on small machines. Less than 36 bits.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Well, in the form 'balanced ternary' the math is described in "The
> Art Of Computer Programming - Vol. 2 Seminumerical Algorithms" by
> Knuth, pg 174 of my 1969 edition.
If I had the book, would I need to ask!
> BTW, the storage elements might be described as 'flip-flap-flops'.
> Really! See page 175
Better keep the books, since what I have seen for in Computer Science
is just RISC computer designs -- YUCK.
I think the only reason RISC machines made a impact is Efective Address
Calculations are fast on a RISC and all the modern addressing modes
use a lot of EFA addition.
Ben
PS.I like 1's compliemnt math but it don't handle multi-presison
operations well and that is needed on small machines. Less than 36 bits.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - Arius - Rick Collins - Jul 22 23:15:00 2005
At 04:30 PM 7/22/2005, you wrote:
>rtstofer wrote:
>
> > Yes, at the moment! I remember reading about this idea many years
> > ago and, at the time, I thought 'so what'? I couldn't represent a
> > trit in hardware so it wasn't particularly useful to know that it
> > would provide a reduced cost.
> >
> > It just seemed strange for someone to bring up this concept after so
> > many years. Even stranger that I actually remembered - sometimes I
> > can't even remember why I went to the garage.
> >
> > But, finding a web page? Incredible!
> >
>
>But just how does one do the math and what about trinary logic
>as compared to binary logic? I have liked the idea of trinary
>logic but have never seen much more on the subject.
>Ben alias woodelf
>Have CPLD , will travel. :)
There have been chips in production for years that use more than two states
per storage element and it is very common right now in Flash memory. I
don't know of any logic that is being implemented in multi-valued
logic. The 8087 FPU used four level logic for its micro code. The levels
were detected by comparitors and translated to binary before being
used. This make the chip small enough to be economically viable.
The current high end flash parts by Intel all use four level storage
elements for two bits per cell. I believe AMD has gone a different route
and actually stores two separate bits using just one cell, I can't recall
how it works, but it is not four level logic.
Back in graduate school, I took a class in multi-valued logic where we
worked with IIL with current mirrors and other types of multi-valued logic
that can be built using transistors. You have to expand your Boolean
algebra to a Post algebra (the general solution of which Boolean is a
special case only using two values) and use different operators. Now that
interconnect is becoming dominant over transistors for using the most space
(that is right, isn't it?), multi-valued logic may start to take off since
it can reduce the number of interconnects. Rick Collins
rick.collins@rick...
Arius - A Signal Processing Solutions Company http://www.arius.com
Specializing in DSP and FPGA design http://www.gnuarm.com
4 King Ave. 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>rtstofer wrote:
>
> > Yes, at the moment! I remember reading about this idea many years
> > ago and, at the time, I thought 'so what'? I couldn't represent a
> > trit in hardware so it wasn't particularly useful to know that it
> > would provide a reduced cost.
> >
> > It just seemed strange for someone to bring up this concept after so
> > many years. Even stranger that I actually remembered - sometimes I
> > can't even remember why I went to the garage.
> >
> > But, finding a web page? Incredible!
> >
>
>But just how does one do the math and what about trinary logic
>as compared to binary logic? I have liked the idea of trinary
>logic but have never seen much more on the subject.
>Ben alias woodelf
>Have CPLD , will travel. :)
There have been chips in production for years that use more than two states
per storage element and it is very common right now in Flash memory. I
don't know of any logic that is being implemented in multi-valued
logic. The 8087 FPU used four level logic for its micro code. The levels
were detected by comparitors and translated to binary before being
used. This make the chip small enough to be economically viable.
The current high end flash parts by Intel all use four level storage
elements for two bits per cell. I believe AMD has gone a different route
and actually stores two separate bits using just one cell, I can't recall
how it works, but it is not four level logic.
Back in graduate school, I took a class in multi-valued logic where we
worked with IIL with current mirrors and other types of multi-valued logic
that can be built using transistors. You have to expand your Boolean
algebra to a Post algebra (the general solution of which Boolean is a
special case only using two values) and use different operators. Now that
interconnect is becoming dominant over transistors for using the most space
(that is right, isn't it?), multi-valued logic may start to take off since
it can reduce the number of interconnects. Rick Collins
rick.collins@rick...
Arius - A Signal Processing Solutions Company http://www.arius.com
Specializing in DSP and FPGA design http://www.gnuarm.com
4 King Ave. 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - woodelf - Jul 23 0:48:00 2005
Arius - Rick Collins wrote:
> The current high end flash parts by Intel all use four level storage
> elements for two bits per cell. I believe AMD has gone a different route
> and actually stores two separate bits using just one cell, I can't recall
> how it works, but it is not four level logic.
But this is FPGA design here, unless you want to go to SMD transistors
and other stuff. :)
> Back in graduate school, I took a class in multi-valued logic where we
> worked with IIL with current mirrors and other types of multi-valued logic
> that can be built using transistors. You have to expand your Boolean
> algebra to a Post algebra (the general solution of which Boolean is a
> special case only using two values) and use different operators. Now that
> interconnect is becoming dominant over transistors for using the most space
> (that is right, isn't it?), multi-valued logic may start to take off since
> it can reduce the number of interconnects.
But out here in the middle of the country all the information I can
find on computers is boolean logic. While trinary logic may save on
interconnects I was thinking it still would make a great computer front
pannel .. toggle switch up +1, toggle switch center 0 toggle switch down
-1 ,Led pannel green led +1, off 0 red -1.
Right now I just working on a 18 bit CPU since FPGA's and CPLD's let you
design non standard word lengths and other features.
Ben alias woodelf.
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> The current high end flash parts by Intel all use four level storage
> elements for two bits per cell. I believe AMD has gone a different route
> and actually stores two separate bits using just one cell, I can't recall
> how it works, but it is not four level logic.
But this is FPGA design here, unless you want to go to SMD transistors
and other stuff. :)
> Back in graduate school, I took a class in multi-valued logic where we
> worked with IIL with current mirrors and other types of multi-valued logic
> that can be built using transistors. You have to expand your Boolean
> algebra to a Post algebra (the general solution of which Boolean is a
> special case only using two values) and use different operators. Now that
> interconnect is becoming dominant over transistors for using the most space
> (that is right, isn't it?), multi-valued logic may start to take off since
> it can reduce the number of interconnects.
But out here in the middle of the country all the information I can
find on computers is boolean logic. While trinary logic may save on
interconnects I was thinking it still would make a great computer front
pannel .. toggle switch up +1, toggle switch center 0 toggle switch down
-1 ,Led pannel green led +1, off 0 red -1.
Right now I just working on a 18 bit CPU since FPGA's and CPLD's let you
design non standard word lengths and other features.
Ben alias woodelf.
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
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Re: Re: Optimal states per bit - Mike Cheponis - Jul 23 2:02:00 2005
On Fri, 22 Jul 2005, woodelf wrote:
> Right now I just working on a 18 bit CPU since FPGA's and CPLD's let you
> design non standard word lengths and other features.
> Ben alias woodelf.
Well, woodelf, I'm not sure why you might consider 18 bits "non standard".
I'm currently a member of a team that is restoring the Computer History
Museum's PDP-1, and it has 18 bits.
18 bits (as well as multiples of 18 bits) is quite natural to me.
Once you see this clearly, you realize the rest of the world got it wrong. Best -Mike
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> Right now I just working on a 18 bit CPU since FPGA's and CPLD's let you
> design non standard word lengths and other features.
> Ben alias woodelf.
Well, woodelf, I'm not sure why you might consider 18 bits "non standard".
I'm currently a member of a team that is restoring the Computer History
Museum's PDP-1, and it has 18 bits.
18 bits (as well as multiples of 18 bits) is quite natural to me.
Once you see this clearly, you realize the rest of the world got it wrong. Best -Mike
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Optimal states per bit - woodelf - Jul 23 2:43:00 2005
Mike Cheponis wrote:
> Well, woodelf, I'm not sure why you might consider 18 bits "non standard".
>
> I'm currently a member of a team that is restoring the Computer History
> Museum's PDP-1, and it has 18 bits.
I've used a PDP8/S and PDP8/e in 1982 and 12 bits are 'standard' for me
but DEC never made a 24 bit CPU. Good luck with restoring the
PDP 1. %^$! now you got me thinking about doing a 24/12 bit processer
but I need more switches and leds and memory since I was building a 18
bitter.
> 18 bits (as well as multiples of 18 bits) is quite natural to me.
>
> Once you see this clearly, you realize the rest of the world got it wrong.
I think going to 8 bit bytes was what the world did wrong, since in
hind-sight 16 bits is too small of a address space for resonable
computing as the 8088/8086 proved. 18 bits is a just right size for a
large controler/ small computer. With the advent of 4 bit TTL MSI logic
the next step would be 20/10 bits for a computer the other size of a
computer I could build from 4,5 bit CPLD bit slices but then I need to
use hexadecimal rather than octal. As pooh would say, "Oh bother". :) > Best -Mike
Thanks for all the help.
Ben alias woodelf
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> Well, woodelf, I'm not sure why you might consider 18 bits "non standard".
>
> I'm currently a member of a team that is restoring the Computer History
> Museum's PDP-1, and it has 18 bits.
I've used a PDP8/S and PDP8/e in 1982 and 12 bits are 'standard' for me
but DEC never made a 24 bit CPU. Good luck with restoring the
PDP 1. %^$! now you got me thinking about doing a 24/12 bit processer
but I need more switches and leds and memory since I was building a 18
bitter.
> 18 bits (as well as multiples of 18 bits) is quite natural to me.
>
> Once you see this clearly, you realize the rest of the world got it wrong.
I think going to 8 bit bytes was what the world did wrong, since in
hind-sight 16 bits is too small of a address space for resonable
computing as the 8088/8086 proved. 18 bits is a just right size for a
large controler/ small computer. With the advent of 4 bit TTL MSI logic
the next step would be 20/10 bits for a computer the other size of a
computer I could build from 4,5 bit CPLD bit slices but then I need to
use hexadecimal rather than octal. As pooh would say, "Oh bother". :) > Best -Mike
Thanks for all the help.
Ben alias woodelf
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Re: Re: Optimal states per bit - Eric Smith - Aug 18 2:21:00 2005
> But right now we are still stuck with binary memory
Quaternary memory has been used in ICs since 1980 or so, originally
with ROMs (e.g., the microcode storage in the Intel 8087 math
coprocessor), and much more recently with Flash memory. In both
cases this is done to reduce the die size and thus the cost per bit.
We're not "stuck with binary".
In principle dynamic RAM could use quaternary as well, but it adds
more complexity than it does with ROM or Flash, so it's not
cost-effective.
Eric
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Quaternary memory has been used in ICs since 1980 or so, originally
with ROMs (e.g., the microcode storage in the Intel 8087 math
coprocessor), and much more recently with Flash memory. In both
cases this is done to reduce the die size and thus the cost per bit.
We're not "stuck with binary".
In principle dynamic RAM could use quaternary as well, but it adds
more complexity than it does with ROM or Flash, so it's not
cost-effective.
Eric
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