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Discussion Groups | FPGA-CPU | timing constraints
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
timing constraints - Rob Finch - Oct 12 3:49:00 2005
I have this line of code in my cpu:
wire [DBW*2-1:0] mul_o = opa * opb;
Is there a way I can tell the synthesizer (XST) that I'm allowing two
clock cycles for it to complete ? Otherwise the timing estimates it
provides will be off.
?
Thanks,
Rob
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
wire [DBW*2-1:0] mul_o = opa * opb;
Is there a way I can tell the synthesizer (XST) that I'm allowing two
clock cycles for it to complete ? Otherwise the timing estimates it
provides will be off.
?
Thanks,
Rob
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
RE: timing constraints - Jeffery, Robert - Oct 12 5:21:00 2005
Hi Rob.
I am not an expert on Xilinx constraints but what you are looking for is
a multicycle path. Looking through the Constraints Guide manual for ISE
7.1 page 107 I found the following:
Multicycle Paths (FROM/THRU/TO)
Definition
Establishes a maximum acceptable time delay between groups of elements
relative to
another timing specification.
UCF Syntax
TIMESPEC "TSid"=FROM "source_group" THRU "timing_point" TO
"destination_group" time [unit];
source_group and destination_group are FFS, RAMS, PADS, LATCHES, or
user-created
groups.
timing_point is an intermediate point as specified by the TPTHRU
constraint on the
Advanced tab window.
You shouldn't need the thru just from to.
Hope that helps.
Cheers.
Robert.
-----Original Message-----
From: fpga-cpu@fpga... [mailto:fpga-cpu@fpga...] On
Behalf Of Rob Finch
Sent: 12 October 2005 08:49
To: fpga-cpu@fpga...
Subject: [fpga-cpu] timing constraints
I have this line of code in my cpu:
wire [DBW*2-1:0] mul_o = opa * opb;
Is there a way I can tell the synthesizer (XST) that I'm allowing two
clock cycles for it to complete ? Otherwise the timing estimates it
provides will be off.
?
Thanks,
Rob To post a message, send it to: fpga-cpu@fpga...
To unsubscribe, send a blank message to:
fpga-cpu-unsubscribe@fpga...
Yahoo! Groups Links
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
I am not an expert on Xilinx constraints but what you are looking for is
a multicycle path. Looking through the Constraints Guide manual for ISE
7.1 page 107 I found the following:
Multicycle Paths (FROM/THRU/TO)
Definition
Establishes a maximum acceptable time delay between groups of elements
relative to
another timing specification.
UCF Syntax
TIMESPEC "TSid"=FROM "source_group" THRU "timing_point" TO
"destination_group" time [unit];
source_group and destination_group are FFS, RAMS, PADS, LATCHES, or
user-created
groups.
timing_point is an intermediate point as specified by the TPTHRU
constraint on the
Advanced tab window.
You shouldn't need the thru just from to.
Hope that helps.
Cheers.
Robert.
-----Original Message-----
From: fpga-cpu@fpga... [mailto:fpga-cpu@fpga...] On
Behalf Of Rob Finch
Sent: 12 October 2005 08:49
To: fpga-cpu@fpga...
Subject: [fpga-cpu] timing constraints
I have this line of code in my cpu:
wire [DBW*2-1:0] mul_o = opa * opb;
Is there a way I can tell the synthesizer (XST) that I'm allowing two
clock cycles for it to complete ? Otherwise the timing estimates it
provides will be off.
?
Thanks,
Rob To post a message, send it to: fpga-cpu@fpga...
To unsubscribe, send a blank message to:
fpga-cpu-unsubscribe@fpga...
Yahoo! Groups Links
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )