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Discussion Groups | FPGA-CPU | [morphware] Low poser going reconfigurable -- Conference announcements
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
[morphware] Low poser going reconfigurable -- Conference announcements - Reiner Hartenstein - Aug 3 3:58:50 2006
Call for Participation:
ISLPED 2006
International Symposium on Low Power Electronics and Design - 2006
October 4-6, 2006, Rottach-Egern, Tegernsee, Germany
http://www.islped.org/
Early registration: before September 1
SBCCI 2006
The 19th Symposium on Integrated Circuits and System Design
August 28 - Sept. 1, 2006, Ouro Preto, Minas Gerais, Brazil
http://www.lecom.dcc.ufmg.br/sbcci/en/sbcci_program.php
PATMOS 2006
International Workshop on Power And Timing,
Optimization and Simulation - 2006
September 13 - 15, Montpellier, France
http://www.lirmm.fr/PATMOS06/
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Have NIOS and Microblaze killed off the fpga-cpu list ? - John Kent - Aug 3 4:17:30 2006
The list has been very quiet these last few months.
Has every one gone off to design Microblaze and NIOS systems ?
Having Linux running on a soft-core CPU is a big plus.
John.
--
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Has every one gone off to design Microblaze and NIOS systems ?
Having Linux running on a soft-core CPU is a big plus.
John.
--
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RE: Have NIOS and Microblaze killed off the fpga-cpu - Hell...@mni.fh-giessen.de - Aug 3 5:33:17 2006
On 03-Aug-2006 John Kent wrote:
> The list has been very quiet these last few months.
> Has every one gone off to design Microblaze and NIOS systems ?
Well, I designed my own 32-bit CPU while teaching a course on
embedded systems hardware. For an instruction simulator see
http://homepages.fh-giessen.de/~hg53/eco32e, for a course
syllabus see http://homepages.fh-giessen.de/~hg53/hes-ss06
(the latter one is in German, I'm sorry). We implemented
the processor, a text display and a keyboard interface on
an XESS XSA-3S1000 board. I intend to add virtual addressing
and a disk interface in order to port some flavour of UNIX
to the system.
Hellwig
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Re: Have NIOS and Microblaze killed off the fpga-cpu - John Kent - Aug 3 9:10:31 2006
Hi Hellwig,
Sounds very good. I wonder if your CPU core as a pipelined RISC machine.
I got a copy of EDK 7.1 through work last year, but thought at the time
it was
a bit of a cop out just dialing up peripherals and plugging them in, but
I had not
done my homework and looked at the peripheral template builder which
supports master / slave operation.
I have been validating my 6809 design against the original chip and have
fixed up a number of bugs which I documented on my web site
http://members.optusnet.com.au/jekent/FPGA.htm
I've designed a number of peripherals such as VDU, ACIA and PIA
and adapted the opencores PS/2 keyboard. It's all glued together manually,
so I'm wondering about adapting the peripherals to Xilinx Programming
Studio.
I've used a single phase clock on my designs. One clock cycle = one
instruction cycle.
PLB and OPB on the other hand use about 6 clock cycles per access, which
must
make the peripheral access pretty slow (or else they use a very fast clock).
I've get the occasion inquiry about the 6809 core, but usually it is for
retro designs.
The 6809 runs with a basic 12.5 Mhz (E) clock on a Spartan2e, so it is
not real fast.
I can run the old Flex operating system on it, but it would be nice to
get a multitasking
operating system like OS9 or Nitros9 running on it. I guess I don't want
to waste
my time hacking a lot of code, for which there is no demand.
I have the Digilent VDEC-1 card which I plan to use on the Spartan 3E
starter board.
The S3E starter board only has 64Mbyte16 bit DDR SDRAM, so I either
design a
DDR SDRAM memory controller and associative cache, or try using multi
bus mastering
under EDK and use microblaze with it's associated memory support.
Obviously an XPS
based design would have a larger market.
Porting Linux to a new processor I would imagine would be a big job. I
bought the
LCC book that Jan recommends on his web site, but there is a lot to work
through in it.
John.
H...@mni.fh-giessen.de wrote:
> On 03-Aug-2006 John Kent wrote:
> > The list has been very quiet these last few months.
> > Has every one gone off to design Microblaze and NIOS systems ?
>
> Well, I designed my own 32-bit CPU while teaching a course on
> embedded systems hardware. For an instruction simulator see
> http://homepages.fh-giessen.de/~hg53/eco32e,
> for a course
> syllabus see http://homepages.fh-giessen.de/~hg53/hes-ss06
>
> (the latter one is in German, I'm sorry). We implemented
> the processor, a text display and a keyboard interface on
> an XESS XSA-3S1000 board. I intend to add virtual addressing
> and a disk interface in order to port some flavour of UNIX
> to the system.
>
> Hellwig
>
> _
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Sounds very good. I wonder if your CPU core as a pipelined RISC machine.
I got a copy of EDK 7.1 through work last year, but thought at the time
it was
a bit of a cop out just dialing up peripherals and plugging them in, but
I had not
done my homework and looked at the peripheral template builder which
supports master / slave operation.
I have been validating my 6809 design against the original chip and have
fixed up a number of bugs which I documented on my web site
http://members.optusnet.com.au/jekent/FPGA.htm
I've designed a number of peripherals such as VDU, ACIA and PIA
and adapted the opencores PS/2 keyboard. It's all glued together manually,
so I'm wondering about adapting the peripherals to Xilinx Programming
Studio.
I've used a single phase clock on my designs. One clock cycle = one
instruction cycle.
PLB and OPB on the other hand use about 6 clock cycles per access, which
must
make the peripheral access pretty slow (or else they use a very fast clock).
I've get the occasion inquiry about the 6809 core, but usually it is for
retro designs.
The 6809 runs with a basic 12.5 Mhz (E) clock on a Spartan2e, so it is
not real fast.
I can run the old Flex operating system on it, but it would be nice to
get a multitasking
operating system like OS9 or Nitros9 running on it. I guess I don't want
to waste
my time hacking a lot of code, for which there is no demand.
I have the Digilent VDEC-1 card which I plan to use on the Spartan 3E
starter board.
The S3E starter board only has 64Mbyte16 bit DDR SDRAM, so I either
design a
DDR SDRAM memory controller and associative cache, or try using multi
bus mastering
under EDK and use microblaze with it's associated memory support.
Obviously an XPS
based design would have a larger market.
Porting Linux to a new processor I would imagine would be a big job. I
bought the
LCC book that Jan recommends on his web site, but there is a lot to work
through in it.
John.
H...@mni.fh-giessen.de wrote:
> On 03-Aug-2006 John Kent wrote:
> > The list has been very quiet these last few months.
> > Has every one gone off to design Microblaze and NIOS systems ?
>
> Well, I designed my own 32-bit CPU while teaching a course on
> embedded systems hardware. For an instruction simulator see
> http://homepages.fh-giessen.de/~hg53/eco32e,
>
> syllabus see http://homepages.fh-giessen.de/~hg53/hes-ss06
>
> (the latter one is in German, I'm sorry). We implemented
> the processor, a text display and a keyboard interface on
> an XESS XSA-3S1000 board. I intend to add virtual addressing
> and a disk interface in order to port some flavour of UNIX
> to the system.
>
> Hellwig
>
> _
--
http://members.optushome.com.au/jekent
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Re: Have NIOS and Microblaze killed off the fpga-cpu - Hell...@mni.fh-giessen.de - Aug 3 12:34:34 2006
Hi John,
On 03-Aug-2006 John Kent wrote:
> I wonder if your CPU core as a pipelined RISC machine.
no, not yet. I did a multi-cycle implementation
because I was not sure how to implement caches
efficiently (and I suspected that the FPGA was
too small to hold all that hardware - but that
was really too cautious, as the device utilization
is now around 5%). The instruction set, however,
is designed to run on a pipelined architecture, so
this is a path I will follow as time permits.
> I've used a single phase clock on my designs. One clock cycle = one
> instruction cycle.
That's really nice. How do you supply instructions
and operands from external memory with that rate? Your
machine has caches? Instructions and data separately?
> Porting Linux to a new processor I would imagine would be a big job. I
> bought the
> LCC book that Jan recommends on his web site, but there is a lot to work
> through in it.
Well, it is relatively easy to write a back-end for LCC.
I did this some time ago for my bigger processor, which
only exists as an instruction set simulator, but not yet
as an FPGA design (http://homepages.fh-giessen.de/~hg53/eco32).
I needed only two weeks for the whole job.
I do not necessarily think of Linux to be run on my
machine (this would request using gcc and its utilities,
and this is really quite a big task). I already had
the old UNIX V7 running on the instruction set simulator,
although it was not very stable and, more important, it
did not use the paging hardware present in the CPU.
The big advantage is kernel size: under 10000 lines...
Hellwig
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On 03-Aug-2006 John Kent wrote:
> I wonder if your CPU core as a pipelined RISC machine.
no, not yet. I did a multi-cycle implementation
because I was not sure how to implement caches
efficiently (and I suspected that the FPGA was
too small to hold all that hardware - but that
was really too cautious, as the device utilization
is now around 5%). The instruction set, however,
is designed to run on a pipelined architecture, so
this is a path I will follow as time permits.
> I've used a single phase clock on my designs. One clock cycle = one
> instruction cycle.
That's really nice. How do you supply instructions
and operands from external memory with that rate? Your
machine has caches? Instructions and data separately?
> Porting Linux to a new processor I would imagine would be a big job. I
> bought the
> LCC book that Jan recommends on his web site, but there is a lot to work
> through in it.
Well, it is relatively easy to write a back-end for LCC.
I did this some time ago for my bigger processor, which
only exists as an instruction set simulator, but not yet
as an FPGA design (http://homepages.fh-giessen.de/~hg53/eco32).
I needed only two weeks for the whole job.
I do not necessarily think of Linux to be run on my
machine (this would request using gcc and its utilities,
and this is really quite a big task). I already had
the old UNIX V7 running on the instruction set simulator,
although it was not very stable and, more important, it
did not use the paging hardware present in the CPU.
The big advantage is kernel size: under 10000 lines...
Hellwig
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Re: Have NIOS and Microblaze killed off the fpga-cpu - Neil Stainton - Aug 11 8:22:43 2006
On Thu, 03 Aug 2006 14:06:08 +0100, John Kent
wrote:
>
> Porting Linux to a new processor I would imagine would be a big job. I
> bought the
> LCC book that Jan recommends on his web site, but there is a lot to work
> through in it.
>
> John.
>
I have been through that excercise, helping a colleague. The LCC code is
pretty impenetrable at first glance, despite the documentation, so the
trick was to make the soft processor look similar to something already
existing. In our case is was a MIPS.
Neil
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