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Discussion Groups | FPGA-CPU | Looking For ALU Design
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Looking For ALU Design - rtstofer - Nov 18 12:28:20 2006
I am looking for a 16 bit 2's complement ALU with
add,subtract,multiply and divide as well as the usual shift and
logical operations. This can be in multiple units like the 'yacc'
project at OpenCores.
The 'yacc' project is very nearly what I need and can be cut down to
serve. But, I was wondering if there might be a source for something
that was already designed for 16 bit.
Blazing, one cycle, speed is not a design goal. I MAY use the 18x18
multiplier of the Spartan 3 for multiply but divide can be iterative
and a simple non-restoring solution would be adequate.
Thanks
Richard
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
add,subtract,multiply and divide as well as the usual shift and
logical operations. This can be in multiple units like the 'yacc'
project at OpenCores.
The 'yacc' project is very nearly what I need and can be cut down to
serve. But, I was wondering if there might be a source for something
that was already designed for 16 bit.
Blazing, one cycle, speed is not a design goal. I MAY use the 18x18
multiplier of the Spartan 3 for multiply but divide can be iterative
and a simple non-restoring solution would be adequate.
Thanks
Richard
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )