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Discussion Groups | FPGA-CPU | BRAM speed [was: Multi-context processor]
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
BRAM speed [was: Multi-context processor] - Tommy Thorn - Dec 4 18:33:03 2006
I just started playing with Xilinx Spartan 3E (speed grade -4) and I was appalled to find
that even with extreme care can I only run the BRAMs at 170 MHz. Anything realistic and
the speed drops much further. This is compared to my age-old Altera Cyclone which happily
ran north of 200 MHz.
You'd need X and A's performance parts (Virtex/Stratix) to get anywhere near 300 MHz. Xilinx Virtex 5 claims 500-550 MHz BRAMs and Altera's Stratix III 600 MHz. I'd love to see how close you can get in practice.
Tommy
----- Original Message ----
From: Jan Gray
To: f...@yahoogroups.com
Sent: Thursday, November 16, 2006 11:16:28 PM
Subject: Re: [fpga-cpu] Re: Multi-context processor
> How fast? I did some quick research on ASIC RAM cycle times recently to
> try to get a ballpark max frequency figure for a new chip. I wanted
> 2.0ns or better, but could only get 3.0 or 2.5 in the stuff that I have
> data on.
> But, in an FPGA, the RAM cycle time is presumably not that important.
> Aren't the carry chains going to kill you? Or something else?
You can do over 300 MHz out of the new BRAMs with the output register
enabled. Other things get in the way up at those speeds.
As for slow adder carry chains, it is possible to ping pong two sets of
adders, each with A and B input registers clocked on altenate cycles, doing
two cycle adds at high speed. It's not area or power efficient, though.
Also interesting is to use the 2 port BRAM as a double clocked
1-cycle-latency 4 port BRAM. Put the multiple thread contexts (register
files) in there. You get 16 sets of 32 registers...
Jan.
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You'd need X and A's performance parts (Virtex/Stratix) to get anywhere near 300 MHz. Xilinx Virtex 5 claims 500-550 MHz BRAMs and Altera's Stratix III 600 MHz. I'd love to see how close you can get in practice.
Tommy
----- Original Message ----
From: Jan Gray
To: f...@yahoogroups.com
Sent: Thursday, November 16, 2006 11:16:28 PM
Subject: Re: [fpga-cpu] Re: Multi-context processor
> How fast? I did some quick research on ASIC RAM cycle times recently to
> try to get a ballpark max frequency figure for a new chip. I wanted
> 2.0ns or better, but could only get 3.0 or 2.5 in the stuff that I have
> data on.
> But, in an FPGA, the RAM cycle time is presumably not that important.
> Aren't the carry chains going to kill you? Or something else?
You can do over 300 MHz out of the new BRAMs with the output register
enabled. Other things get in the way up at those speeds.
As for slow adder carry chains, it is possible to ping pong two sets of
adders, each with A and B input registers clocked on altenate cycles, doing
two cycle adds at high speed. It's not area or power efficient, though.
Also interesting is to use the 2 port BRAM as a double clocked
1-cycle-latency 4 port BRAM. Put the multiple thread contexts (register
files) in there. You get 16 sets of 32 registers...
Jan.
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )