Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
See Also
Discussion Groups | FPGA-CPU | Timing Constraints
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Timing Constraints - rtstofer - Dec 22 11:13:40 2006
I'm working on a project with the Spartan 3 Starter Board and the
Xilinx WebPack ISE version 8.2
As I look over the timing results, there are lengthy delays in the
paths containing input switches (toggle switches) and digit/segment
outputs to 7 segment displays.
I certainly don't care about the timing of these signals and was
thinking about using TIG (totally ignore) as a timing constraint in
the .UCF file.
I could also latch the switches to synchronize with the clock but,
ultimately, everything is synchronized to the clock.
Is there any reason to include delays associated with pins such as
these? Or, is it appropriate to ignore the delays?
Thanks
Richard
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Xilinx WebPack ISE version 8.2
As I look over the timing results, there are lengthy delays in the
paths containing input switches (toggle switches) and digit/segment
outputs to 7 segment displays.
I certainly don't care about the timing of these signals and was
thinking about using TIG (totally ignore) as a timing constraint in
the .UCF file.
I could also latch the switches to synchronize with the clock but,
ultimately, everything is synchronized to the clock.
Is there any reason to include delays associated with pins such as
these? Or, is it appropriate to ignore the delays?
Thanks
Richard
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Timing Constraints - Paul Davis - Dec 22 11:42:41 2006
rtstofer wrote:
> Is there any reason to include delays associated with pins such as
> these? Or, is it appropriate to ignore the delays?
You always need to put something in your constraints, or you'll end up
with a report which gives misleading maximum delays, or even a timing
failure. How exactly you do it doesn't really matter. I generally tend
to false path/TIG ('Timing', I think, rather than 'Totally') unimportant
async signals. On the other hand, if you actually specify a real nominal
delay, then the tools will at least try to meet this delay, and you'll
get a nice report on what the real delay actually is.
Paul
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Is there any reason to include delays associated with pins such as
> these? Or, is it appropriate to ignore the delays?
You always need to put something in your constraints, or you'll end up
with a report which gives misleading maximum delays, or even a timing
failure. How exactly you do it doesn't really matter. I generally tend
to false path/TIG ('Timing', I think, rather than 'Totally') unimportant
async signals. On the other hand, if you actually specify a real nominal
delay, then the tools will at least try to meet this delay, and you'll
get a nice report on what the real delay actually is.
Paul
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Timing Constraints - rtstofer - Dec 22 12:03:48 2006
--- In f...@yahoogroups.com, Paul Davis wrote:
>
> rtstofer wrote:
>
> > Is there any reason to include delays associated with pins such as
> > these? Or, is it appropriate to ignore the delays?
>
> You always need to put something in your constraints, or you'll end up
> with a report which gives misleading maximum delays, or even a timing
> failure. How exactly you do it doesn't really matter. I generally tend
> to false path/TIG ('Timing', I think, rather than 'Totally')
unimportant
> async signals. On the other hand, if you actually specify a real
nominal
> delay, then the tools will at least try to meet this delay, and you'll
> get a nice report on what the real delay actually is.
>
> Paul
>
Where can I find an example of specifying the timing of an external
static RAM? I'm not using it for this project (yet) but it seems
reasonable to specify the setup and access time delays. But, for all
the books I have, nothing is ever said about timing constraints.
Sure, they have all the priority encoders, decoders and state machines
a person could use in VHDL or Verilog. But, nothing about timing...
I haven't spent much time with the Constraints Guide but what I have
seen is more like a datasheet than an app note.
Richard
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>
> rtstofer wrote:
>
> > Is there any reason to include delays associated with pins such as
> > these? Or, is it appropriate to ignore the delays?
>
> You always need to put something in your constraints, or you'll end up
> with a report which gives misleading maximum delays, or even a timing
> failure. How exactly you do it doesn't really matter. I generally tend
> to false path/TIG ('Timing', I think, rather than 'Totally')
unimportant
> async signals. On the other hand, if you actually specify a real
nominal
> delay, then the tools will at least try to meet this delay, and you'll
> get a nice report on what the real delay actually is.
>
> Paul
>
Where can I find an example of specifying the timing of an external
static RAM? I'm not using it for this project (yet) but it seems
reasonable to specify the setup and access time delays. But, for all
the books I have, nothing is ever said about timing constraints.
Sure, they have all the priority encoders, decoders and state machines
a person could use in VHDL or Verilog. But, nothing about timing...
I haven't spent much time with the Constraints Guide but what I have
seen is more like a datasheet than an app note.
Richard
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: Timing Constraints - Paul Davis - Dec 22 12:33:15 2006
rtstofer wrote:
> Where can I find an example of specifying the timing of an external
> static RAM? I'm not using it for this project (yet) but it seems
> reasonable to specify the setup and access time delays. But, for all
> the books I have, nothing is ever said about timing constraints.
>
> Sure, they have all the priority encoders, decoders and state machines
> a person could use in VHDL or Verilog. But, nothing about timing...
> I haven't spent much time with the Constraints Guide but what I have
> seen is more like a datasheet than an app note.
The constraints guide has it all, but you'll have to wade through it a
few times to get any understanding of it. The best beginner source I
found was a Xilinx PowerPoint presentation years ago, which contained
pretty much everything you needed to know, with examples. I'm afraid
that I don't have it, but someone on comp.arch.fpga might remember it.
Paul
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
> Where can I find an example of specifying the timing of an external
> static RAM? I'm not using it for this project (yet) but it seems
> reasonable to specify the setup and access time delays. But, for all
> the books I have, nothing is ever said about timing constraints.
>
> Sure, they have all the priority encoders, decoders and state machines
> a person could use in VHDL or Verilog. But, nothing about timing...
> I haven't spent much time with the Constraints Guide but what I have
> seen is more like a datasheet than an app note.
The constraints guide has it all, but you'll have to wade through it a
few times to get any understanding of it. The best beginner source I
found was a Xilinx PowerPoint presentation years ago, which contained
pretty much everything you needed to know, with examples. I'm afraid
that I don't have it, but someone on comp.arch.fpga might remember it.
Paul
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )