Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Discussion Groups
Discussion Groups | FPGA-CPU | New Project
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Re: New Project - Ben Franchuk - Feb 25 23:53:00 2001
|
wrote: > The CPU I will be developing will be a stack-based processor designed > to be efficient at executing IPS (a Forth-like language and OS). It > will be intended for use in high-radiation environments, and will be > targeted for an Actel SX-series part of 32K "gates" (or 16K gates if > I can fit it into a device that small). The only problem that may be a issue is Input/Output pins. This may be a factor if you have not I/O well defined in the initial stages, or you have a specific package in mind like a 84pin PLCC.All forth CPU's that I have seen have are small so XXK gates is not a problem. I do have one question how ever: Will the cpu have redundant logic or just assume the RAD tolerance of the hardware is sufficient to keep the cpu in good health? Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
New Project - Author Unknown - Feb 28 22:15:00 2001
|
Hello! Like many of you, I am new to designing a CPU and putting it into an FPGA. The CPU I will be developing will be a stack-based processor designed to be efficient at executing IPS (a Forth-like language and OS). It will be intended for use in high-radiation environments, and will be targeted for an Actel SX-series part of 32K "gates" (or 16K gates if I can fit it into a device that small). The intent is that it use external SRAM in a Triple Mode Redundant scheme, and that it incorporate a fair amount of trivial I/O for external devices. And that it boot in a ROMLESS mode. And... I have used FPGAs before, mostly QuickLogic, some of which are now in high-radiation environments (the AO-40 spacecraft for example, see www.amsat.org). The driver for this development is the high cost of rad-hard devices and the fact that AMSAT, for whom I am a volunteer engineer, is a non- profit group dependent upon donations for its work. The core will be open-source when it is finally working. Initial development will be with a Xilinx Spartan-2, for its reprogrammability. I am not sure what input method I will use. I am most comfortable with schematics, but may be forced to Verilog or VHDL. Efficiency is important to the extent that the CPU plus reasonable I/O must fit into a single FPGA. Performance isn't much of an issue as our current spacecraft controllers are based on the Sandia-processed (e.g., rad hard) CDP1802 running at a blistering 100k instructions per second... If any of you know of any particular quirks or ??? about putting a CPU into an Actel SX-series FPGA, please let me know! Incidentally, I downloaded the Webpack tools and upon running them my computer (Dell Inspiron 7500, 600 MHz PIII, 192MB RAM, Win98SE) refused to boot and I had to reformat the hard drive! This happened twice, so I am pretty skittish about Webpack. Anyone else have problems with it? (I have successfully used Foundation 2.1i on another computer, so I was surprised by the Webpack problem.) Thanks in advance, Lyle Johnson, KK7P |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: New Project - Mike Butts - Mar 1 1:45:00 2001
|
Excellent!!! A very fine idea. I have long been a Forth fan ever since porting FIG-Forth way back when. I'm also a ham, active on OSCAR-13 back when it was up (66 countries worked on Mode-B). So you've pushed several of my happy buttons. I can't tell you anything about the Actel chips, being strictly of the RAM reconfigurable persuasion. But I was associated with a research project at Stanford a few years ago that is still working, dealing with Xilinx-type SRAM FPGAs in space. They gave a paper at the FPGA conference in Monterey earlier this month: "A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations. Wei-Je Huang and Edward J. McCluskey, Stanford University." http://crc.stanford.edu/projects/argos.html "Reconfigurable computing using FPGAs is another part of the Stanford ARGOS project. The COTS board has a Xilinx 4003 FPGA that can be reprogrammed during the mission. We will use this feature for testing the FPGA, testing other parts of the system if possible, and tolerating the faults occurring in the FPGA. FPGAs add flexibility to the system, and also, it is a good opportunity to test these devices in a space environment." 73 de KC7IT |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
RE: New Project - Lyle Johnson - Mar 1 11:32:00 2001
|
Hello Mike! I have looked up a lot of references to using Xilinx in space. The issue tends to get complex as one must reliably determine if any of the configuration RAM bits have been toggled by an ion, and then reconfigure. A non-RAM-based technology will be best for our needs -- unfortunately :-( Our mission doesn't need reconfigurability. Indeed, we are only seeking to replace a humble CPU with another that we won't have to worry about the source disappearing. The reason for using IPS is to re-use the software components from OSCAR-13, the extreme memory efficiency of FOrth for control systems, and the intolerable cost of rad-hard RAM. The 32k "gate" Actel part costs $4,700 in single quantity, so the CPU has to be very straightforward to fit in this space and still have room for necessary I/O (perhaps multiple SPI interfaces; CAN is likely too complex to fit) and the digital portion of the uplink demodulator (differentially encoded BPSK at low bit rates, requires a DPLL to acquire the clock, remove the bits, then detect certain sync vectors, etc.). The 32k gate Actel part has 1800 flip-flops and 2800 simple combinational cells. This is not the rich fabric of powerful Xilinx cells, or QuickLogic cells, but rather very simple cells. This may be a serious challenge! The plan is to make a PCB with the necessary I/O and put a Spartan-2 100K gate device on it, along with a 208 "pin" TQFP socket wired for the Actel device. We prototype the CPU and get it working with Xilinx, then fit and mess around until we have something that appears to fit into the Actel, verify it once more in the Xilinx, then burn an Actel commercial part, test, iterate, etc. 73 de KK7P |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: New Project - Author Unknown - Mar 1 11:45:00 2001
|
--- In fpga-cpu@y..., "Lyle Johnson" <wa7gxd@e...> wrote: > The 32k gate Actel part has 1800 flip-flops and 2800 simple combinational > cells. This is not the rich fabric of powerful Xilinx cells, or QuickLogic > cells, but rather very simple cells. This may be a serious challenge! Oops. Make that 1080 Flip-Flops and 2880 combinatorial cells. Lyle |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: New Project - Author Unknown - Mar 1 11:53:00 2001
|
--- In fpga-cpu@y..., Ben Franchuk <bfranchuk@j...> wrote: > The only problem that may be a issue is Input/Output pins. This may be > a factor if you have not I/O well defined in the initial stages, or > you have a specific package in mind like a 84pin PLCC.All forth CPU's > that I have seen have are small so XXK gates is not a problem. We're using the 208-pin package. This has plenty of I/O for our needs. It is also the only package the rad-tolerant device comes in! > I do have one > question how ever: Will the cpu have redundant logic or just assume > the RAD tolerance of the hardware is sufficient to keep the cpu in good health? The Rad Tolerant version of the A54SX includes triple mode redunancy (TMR) on all internal flip-flops. Hence, Actel has put in the redundancy in a way that is transparent to the implementer. One still has to be careful of course, and clock flip-flops with their own data when they are not otherwise being used to refresh corrupted bits before they can overcome the TMR correction, etc. The (external) memory system will be based on TMR, using three (3) physical RAM chips in a majority-vote logic scheme. I have already done this with other flight computers not based on rad-tolerant silicon in the CPU, FPGA or memory (see, for example, http://www.amsat.org/amsat/articles/g3ruh/124.html). Regards, Lyle |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
New Project - Can Koklu - Oct 26 9:07:00 2004
|
Hello everyone, I'm a 4th year student in Carleton University (Ottawa, ON). As our 4th year project me and my friends decided to take up the project of FPGA based JVM design. Our project proposal is here: http://cankoklu.com/notes/proj_01_proposal.pdf The problem i sI am completely lost on how to start the FPGA design part. I have read a whole bunch of stuff but I still can't get started.. I would really appreciate any and all advice on how to get started. Thanks, Can Koklu |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: New Project - Martin Schoeberl - Nov 6 13:48:00 2004
|
Hi Can, an interesting project. Perhaps you have already found it, but I want to provide you a link to a Java processor in an FPGA: http://www.jopdesign.com/ to get you started. Keep me informed about your project and best wishes, Martin ----- Original Message ----- From: "Can Koklu" <> To: <> Sent: Tuesday, October 26, 2004 3:07 PM Subject: [fpga-cpu] New Project > Hello everyone, > > I'm a 4th year student in Carleton University (Ottawa, ON). As our > 4th year project me and my friends decided to take up the project of > FPGA based JVM design. > > Our project proposal is here: > http://cankoklu.com/notes/proj_01_proposal.pdf > > The problem i sI am completely lost on how to start the FPGA design > part. I have read a whole bunch of stuff but I still can't get started.. > > I would really appreciate any and all advice on how to get started. > > Thanks, > Can Koklu > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )