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Hello,

I came across this old posting for the POP-11, but the original
URL no longer works. I'd really like to get the
VHDL source code for the POP-11 project if possible.
Can someone send me an updated URL?

Thanks in Advance,
Scott
-- In Oct 6, 2004, Naohiko Shimizu-san wrote:
>
> Hi all,
>
> I and my student Mr.Iida placed a PDP11/40 compatible CPU source
> code on our web site. (POP11/40) That includes, CPU, serial
> interface and RK to IDE protocol converter.
>
> We used the processor with ALTERA's EP1C3 or EP1K100.
> Whole logic to boot UNIX V6 is fit within 3000 LUT on ALTERA.
>
> I hope you enjoy it.
>
> http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html
>
> Naohiko Shimizu
>


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Scott wrote:
> I came across this old posting for the POP-11, but the original
> URL no longer works. I'd really like to get the
> VHDL source code for the POP-11 project if possible.
> Can someone send me an updated URL?

It wasn't written in VHDL or Verilog. It was designed in sfl, then
compiled into Verilog using sfl2vl, a tool only available as a
Windows executable.

I haven't seen the output of sfl2vl, but I doubt that it was
very human-friendly.


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Hi Eric & Scott,

I found a link to the SFL to Verilog program, but it appears to be at

http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html

which is the same university as the POP11/40 and the link no longer works

Dr. Naohiko Shimizu seems to have set up a web site here:

http://www.ip-arch.jp/indexe.html

There is a not for profit version of his SFL to Verilog translator
but I can't see the POP11/40 design.

John.

Eric Smith wrote:
>
> Scott wrote:
> > I came across this old posting for the POP-11, but the original
> > URL no longer works. I'd really like to get the
> > VHDL source code for the POP-11 project if possible.
> > Can someone send me an updated URL?
>
> It wasn't written in VHDL or Verilog. It was designed in sfl, then
> compiled into Verilog using sfl2vl, a tool only available as a
> Windows executable.
>
> I haven't seen the output of sfl2vl, but I doubt that it was
> very human-friendly.

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent


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Hi Eric,

SFL looks like an interesting language. I have the sfl2vl
tool installed, but I have not tried any test cases.
Do you know where I can find the POP-11 SFL source?

Regards,
Scott

--- In f...@yahoogroups.com, "Eric Smith" wrote:
>
> It wasn't written in VHDL or Verilog. It was designed in sfl, then
> compiled into Verilog using sfl2vl, a tool only available as a
> Windows executable.
>
> I haven't seen the output of sfl2vl, but I doubt that it was
> very human-friendly.
>



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Hi,

Dr. Shimizu says that the website where the POP-11 source code
is located is down for maintenance and it will be available again
next week.

In the meantime, I have decided to write my own PDP-11 VHDL model
from scratch. I currently have completed the instruction decoder.

Regards,
Scott



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Hey John,

Cool. There is an email address for Dr. Shimizu at the bottom
of that page, so I have written to him asking if the POP-11
SFL code is still available. I had previously written to him
at his Tokai University address, but I received no response
from that address.

In the meantime, last night I sat down and wrote the VHDL
case statements for a PDP-11/40 instruction decoder.
So I am on my way to writing my own model :-)
I'll let you know how it goes.

Regards,
Scott L Baker

--- In f...@yahoogroups.com, John Kent wrote:
>
> Hi Eric & Scott,
>
> I found a link to the SFL to Verilog program, but it appears to be at
>
> http://shimizu-lab.dt.u-tokai.ac.jp/pgm/sfl2vl/index.html
>
> which is the same university as the POP11/40 and the link no longer
works
>
> Dr. Naohiko Shimizu seems to have set up a web site here:
>
> http://www.ip-arch.jp/indexe.html
>
> There is a not for profit version of his SFL to Verilog translator
> but I can't see the POP11/40 design.
>
> John.
> --- In f...@yahoogroups.com, "Scott" wrote:
>>
>> Hi Eric,
>>
>> SFL looks like an interesting language. I have the sfl2vl
>> tool installed, but I have not tried any test cases.
>> Do you know where I can find the POP-11 SFL source?
>>
>> Regards,
>> Scott
>>



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--- In f...@yahoogroups.com, "Scott" wrote:
>
> Hey John,
>
> Cool. There is an email address for Dr. Shimizu at the bottom
> of that page, so I have written to him asking if the POP-11
> SFL code is still available. I had previously written to him
> at his Tokai University address, but I received no response
> from that address.
>
> In the meantime, last night I sat down and wrote the VHDL
> case statements for a PDP-11/40 instruction decoder.
> So I am on my way to writing my own model :-)
> I'll let you know how it goes.
>
> Regards,
> Scott L Baker

I am interested in your project and would like to tag along. My first
question: is there a complete suite of software available for the CPU?

Please keep the group posted!
Richard



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Richard,

On Tue, 2007-08-21 at 13:11 +0000, rtstofer wrote:

> I am interested in your project and would like to tag along. My first
> question: is there a complete suite of software available for the CPU?

you can run UNIX 7th Edition on a PDP-11/40. The original
distribution tape is available from http://www.tuhs.org

You must configure the software before you can use it on
an 11/40. This is best done on a running system. I have
V7 running on a simulator (I'm in the process of porting
it to my own 32-bit RISC CPU). All the software you need
(including V7 and the simulator) can be downloaded from
my site http://homepages.fh-giessen.de/~hg53/pdp11-unix

If you have any questions, feel free to ask.

Best regards,
Hellwig


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Hellwig,

Thanks for the links. I have absolutely NO experience with the PDP-11
so these links will give me a start.

Richard



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It's back! See http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html

This time I'll download it and put it on a CD! Perhaps this winter
I'll get around to converting it to run on a Spartan 3 Starter Board.
If I read the info correctly, it was built on a chip with 100k gates
so a 1M gate Spartan 3 ought to work!

Richard



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Hi,

There's lot's of software available for the PDP-11, but
probably not much that has been written recently.

Since I've decided to write my own PDP-11 VHDL model.
I would really like to find some test programs.

If anyone has any pointers to CPU POST or other PDP-11
diagnostic programs, please let me know.

Thanks,
Scott
> --- In f...@yahoogroups.com, "Scott" wrote:

> > ... last night I sat down and wrote the VHDL
> > case statements for a PDP-11/40 instruction decoder.
> > So I am on my way to writing my own model :-)
> > I'll let you know how it goes.
> >
> > Regards,
> > Scott L Baker

--- In f...@yahoogroups.com, "rtstofer" wrote:
>
> I am interested in your project and would like to tag along.
> My first question: is there a complete suite of software
> available for the CPU?
>
> Please keep the group posted!
> Richard
>



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Hi,

My PDP-11 VHDL model just passed this very simple test..
So at least a few instructions seem to be working OK.. :-)
Now on to the fun part... implementing the operand
addressing modes. :-)

Regards,
Scott

-------------- cut here -------------

;-------------------------------------------------------------------
; pdp11 .. A very simple test .. branches and condition codes
;-------------------------------------------------------------------

nop
nop

sen
bpl err_1$

sez
bne err_1$

sev
bvc err_1$

sec
bcc err_1$

cln
bmi err_1$

clz
beq err_1$

clv
bvs err_1$

clc
bcs err_1$

scc
ccc

br all_OK$

scc
nop

all_OK$: halt

nop
nop

err_1$: br err_1$

nop
nop

-------------- cut here -------------
--- In f...@yahoogroups.com, "Scott" wrote:
>
> Hi,
>
> There's lot's of software available for the PDP-11, but
> probably not much that has been written recently.
>
> Since I've decided to write my own PDP-11 VHDL model.
> I would really like to find some test programs.
>
> If anyone has any pointers to CPU POST or other PDP-11
> diagnostic programs, please let me know.
>
> Thanks,
> Scott
> > --- In f...@yahoogroups.com, "Scott" wrote:
>
> > > ... last night I sat down and wrote the VHDL
> > > case statements for a PDP-11/40 instruction decoder.
> > > So I am on my way to writing my own model :-)
> > > I'll let you know how it goes.
> > >
> > > Regards,
> > > Scott L Baker
>
> --- In f...@yahoogroups.com, "rtstofer" wrote:
> >
> > I am interested in your project and would like to tag along.
> > My first question: is there a complete suite of software
> > available for the CPU?
> >
> > Please keep the group posted!
> > Richard
>


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Scott wrote:
>
> Hi,
>
> My PDP-11 VHDL model just passed this very simple test..
> So at least a few instructions seem to be working OK.. :-)
> Now on to the fun part... implementing the operand
> addressing modes. :-)
>
> Regards,
> Scott
>
> -------------- cut here -------------

It don't work on glass TTY's
>
> ;----------------------------------------------------------
> ; pdp11 .. A very simple test .. branches and condition codes
> ;----------------------------------------------------------
>
> nop
> nop
>
> sen
> bpl err_1$
>
> sez
> bne err_1$
>
> sev
> bvc err_1$
>
> sec
> bcc err_1$
>
> cln
> bmi err_1$
>
> clz
> beq err_1$
>
> clv
> bvs err_1$
>
> clc
> bcs err_1$
>
> scc
> ccc
>
> br all_OK$
>
> scc
> nop
>
> all_OK$: halt
>
> nop
> nop
>
> err_1$: br err_1$
>
> nop
> nop

> -------------- cut here -------------

Good luck with the design. Now all you need is a few
leds - halt/run/ and you can test the hardware.

The only problem I can see is the PDP-11 instruction
set is still copy written.
Ben alias Woodelf.


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Hi Woodelf

Love the name :-)

I think I've seen the discussion on copyright of instructions before on
this list,
but I can't remember what the out come was. I should look back on the list.
Does that mean an emulator that uses the PDP-11 instruction set is also
violating copyright ?
What if I modify how the instructions work some how that maintains
compatibility,
or maybe add a segment register or something. Is that violating copyright ?

John.

> Good luck with the design. Now all you need is a few
> leds - halt/run/ and you can test the hardware.
>
> The only problem I can see is the PDP-11 instruction
> set is still copy written.
> Ben alias Woodelf.
>
> __._,
>
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent


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That should be an FAQ.
The bottom line:

- ISAs not protected at all
- Implementations covered by copyright. So do not use the original
schematics as a basis for your design.
- Implementaion concepts, ideas etc. can be covered by patents.
Original PDP11 patents are expired by now. So it must be possible to do an
patent free implementation.
However, you are probably using more modern implementation styles in your
new design so some of
your design decision might be covered by other patents. On the other hand,
you are unlikely to be sued
by ARM because your PDP11 implementation uses a patented register file idea
from an ARM patent.

Kolja Sulimma, NAL (not a lawyer)
[Non-text portions of this message have been removed]


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On Wed, 2007-08-22 at 19:06 +1000, John Kent wrote:

> Does that mean an emulator that uses the PDP-11 instruction set is
> also violating copyright ?

I don't believe this to be true regarding all the PDP-11
simulators (even commercial ones) out there.

Hellwig



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2007/8/22, Hellwig Geisse :

> > Does that mean an emulator that uses the PDP-11 instruction set is
> > also violating copyright ?
> I don't believe this to be true regarding all the PDP-11
> simulators (even commercial ones) out there´,

An instruction set architecture is no "work" in the sense of copyright law.
Copyright simply does not apply to it.

The document describing the ISA however is copyrighted. Do not
distribute it with your emulater/core/whatever. Instead write your
own.

A software emulator definitely does not use any implementation
techniques from the original hardware, so neither copyright on the
design nor ISA/CPU/hardware patents apply.

Be aware however that there are zillions of patents on fast emulation
techniques. I doubt that you can write a decent emulator without
violating these. Therefore you should move your development department
to Europe where there are no software patents.

Kolja Sulimma



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Kolja Sulimma wrote:

> Therefore you should move your development department
> to Europe where there are no software patents.

Not so. In British patent law, for example, you can file a "software"
patent as long as you can demonstrate that it has a technical effect,
isn't simply automation, isn't just an algorithm implementation, and so
on. There is no fundamental distinction as to *how* your idea is
implemented; if you've got a patentable idea that you happen to
implement in software, then that's fine. Do a search - you should find a
lot of British case law on this subject, as well as real patents.

A UK software patent is a lot more difficult to file than a US software
patent, but it's still a software patent. This is acceptable to the
European patent office, and so I assume (in fact, I'm pretty sure) that
other European countries have similar national regulations.

The recent opposition to the European patent directive was completely
misguided. It wouldn't have *allowed* software patents; it would simply
have harmonised existing national laws, which *already* allow software
patents. It was a great example of how to fool a lot of people by
shouting loudly enough, and not bothering to check your facts.

Anyway, the premise that you can avoid US patents by developing in
Europe is misguided. It's true that a US patent only gives legal
protection in the US, but very few non-US companies would be happy to
exclude the US as a market. If you develop in Europe, you need to watch
out for US patents, or you potentially lose half your market. The fact
that US patent X is a half-arsed and pointless waste of space is just
irrelevant; the US courts can stop you selling in the US, and can charge
you lots of money for the privilege. There's also the outside
possibility that the US could attempt to pursue you via international
trade agreements even if you don't sell in the US.

No, I'm not a lawyer either, but I've spent a lot of money on patent
lawyers, and spent a lot of time drafting patents, and reading case law.



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On Wed, 22 Aug 2007 00:35:19 -0600, you wrote:

>
>The only problem I can see is the PDP-11 instruction
>set is still copy written.
>

How can that be after so many years, now? Wasn't the pdp-11/20 first
shipped out in early 1970?? That's 37 years and more.

Jon



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Paul Davis wrote:

> No, I'm not a lawyer either, but I've spent a lot of money on patent
> lawyers, and spent a lot of time drafting patents, and reading case law.

Well the real point is the PDP-11 is still a commercial product
so I am not sure just when the patents expire. How ever since most
FPGA products never make it to the commercial market I doubt if
you will have problems for your own use. If you do want to be different
- clone a Soviet Union clone of of the PDP-11.


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2007/8/22, Jonathan Kirwan :

> On Wed, 22 Aug 2007 00:35:19 -0600, you wrote:
>
> >
> >The only problem I can see is the PDP-11 instruction
> >set is still copy written.
> > How can that be after so many years, now? Wasn't the pdp-11/20 first
> shipped out in early 1970?? That's 37 years and more

Copyright currently lasts 75 years from the death of the author.
It's regularly extended to prevent Mickey Mouse from becoming public domain.
Fortunately copyright does not apply to ISAs.

Kolja Sulimma



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Jonathan Kirwan wrote:

> How can that be after so many years, now? Wasn't the pdp-11/20 first
> shipped out in early 1970?? That's 37 years and more.

Micky Mouse is still patented and he came out in the 40's.
I think off hand what was patented was the PC is used as general
index register - not a special register as before.

> Jon
PS. Disney is still pushing for longer time for patents.



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I just started playing with POP-11 (now that the site is back up) and
one of the neat things is that the sfl2vl utility also has an sfl2vh
funtion which creates VHDL from SFL.

I have converted POP-11 to VHDL but it is going to take a lot of
thought to figure out how to port it to the Spartan III Starter Board.
It would help if I knew ANYTHING about the PDP-11/40 but alas...

Richard
--- In f...@yahoogroups.com, "Scott" wrote:
>
> Hello,
>
> I came across this old posting for the POP-11, but the original
> URL no longer works. I'd really like to get the
> VHDL source code for the POP-11 project if possible.
> Can someone send me an updated URL?
>
> Thanks in Advance,
> Scott
>


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No, no, no.

Patents and Copyright are completely different things. Almost unrelated.
Mickey Mouse never was patented and couldn't be so.
Patents expire within a few decades, copyrights last a lot longer.
Kolja Sulimma

2007/8/22, woodelf :
> Jonathan Kirwan wrote:
>
> > How can that be after so many years, now? Wasn't the pdp-11/20 first
> > shipped out in early 1970?? That's 37 years and more.
>
> Micky Mouse is still patented and he came out in the 40's.
> I think off hand what was patented was the PC is used as general
> index register - not a special register as before.
>
> > Jon
> PS. Disney is still pushing for longer time for patents.



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Kolja Sulimma wrote:

> Patents and Copyright are completely different things. Almost unrelated.
> Mickey Mouse never was patented and couldn't be so.
> Patents expire within a few decades, copyrights last a lot longer.

I say 'much the same', just one is for art and writing and one is for technology.

> Kolja Sulimma

Since I found FPGA's too small for a random logic cpu design I have created.
I ended up using the internal ram as micro-code to get it all to fit.

I have not looked into using them recently. Right now I am looking doing a 2901
74LSXXX design for my cpu and am trying to get the right PCB software.

Remember a REAL 11 has a front panel and that takes up a lot I/O pins.
Also UNIX may require 1) a memory management unit 2) Floating point too.
I think there are of PDP-11 chips out there that are still around because
they never had those features.


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> Since I found FPGA's too small for a random logic cpu design I have
created.
> I ended up using the internal ram as micro-code to get it all to fit.
>
> I have not looked into using them recently. Right now I am looking
doing a 2901
> 74LSXXX design for my cpu and am trying to get the right PCB software.
>
> Remember a REAL 11 has a front panel and that takes up a lot I/O pins.
> Also UNIX may require 1) a memory management unit 2) Floating point too.
> I think there are of PDP-11 chips out there that are still around
because
> they never had those features.
>

The POP-11 has an MMU but no floating point. The author has Unix
running so floating point must not be a requirement. It certainly
isn't a requirement for Linux as that runs on a lot of ARM9 chips
without FPUs.

I had thought to use IO Expanders (SPI <-> a lot of pins) to handle
the LEDs and switches. After all, I can send the values far faster
than the eye can see and LEDs only mean anything when the CPU is
stopped. Within a mS I could easily update the entire display and
read all the switches. SPI only requires 3 wires (Clk, MOSI, MISO)
plus one device select per gadget. Or use an external selector so 3
pins select 8 devices - leave one empty to deselect the bus.

I have used SPI to a 16 hex digit display (MAX6954) for another
project and it worked well. I have chips for SPI to matrix LEDs (8x8
dual color) and I have already done 16 console switches to SPI
(MCP23S17). All of this is trivial compared to getting the CPU to
function.

The Z80 core (T80) fits easily in a 300k gate device and a complete
minicomputer with all of the IO devices (card reader, printer,
typewriter, keyboard, disk drive) fits easily in a 1M gate Spartan 3.
In fact, the minicomputer only uses 300k gates plus every byte of the
BlockRAM.

It looks like the POP11 fits in 100k gates based on using the EP1K100
or 2910 LEs (whatever they are defined to be) for the EP1C3. So,
despite the fact the code (in VHDL) is about 9000 lines, it fits in a
fairly small device.

A 1M gate Sparten 3 in HUGE (think in terms of 10 PDP-11/40s) and the
Starter Board is cheap at $149 (for the 1M version)
http://digilentinc.com/Products/Detail.cfm?Prod=S3BOARD

I like the 2901 stuff and I certainly know how to do the microcode but
you can use exactly the same approach using an FPGA. It isn't
commonly done that way but there is no reason you can't define a very
wide array by some arbitary length and code the bits. In fact, that
part is easy because you can define them in INIT strings in the
configuration file (*.ucf) so you can twiddle the microcode without
recompiling the entire VHDL (maybe). You can also use the BlockRAM to
store the microcode and initialize it the same way. Or, you can store
the microcode on a SD/MMC card and load it at boot time. This is a
neat option because all microcoding is done without recompiling anything.

Richard



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rtstofer wrote:

> It looks like the POP11 fits in 100k gates based on using the EP1K100
> or 2910 LEs (whatever they are defined to be) for the EP1C3. So,
> despite the fact the code (in VHDL) is about 9000 lines, it fits in a
> fairly small device.

> I like the 2901 stuff and I certainly know how to do the microcode but
> you can use exactly the same approach using an FPGA. It isn't
> commonly done that way but there is no reason you can't define a very
> wide array by some arbitary length and code the bits. In fact, that
> part is easy because you can define them in INIT strings in the
> configuration file (*.ucf) so you can twiddle the microcode without
> recompiling the entire VHDL (maybe). You can also use the BlockRAM to
> store the microcode and initialize it the same way. Or, you can store
> the microcode on a SD/MMC card and load it at boot time. This is a
> neat option because all microcoding is done without recompiling anything.

I used the other brand of FPGA's and was doing my logic design as schematic
entry. I had 750 CLB's and 256x32 ram so I configured the random logic
to fit in the ram to save space. This was a compile time option.
Even so the routing is what killed the project. It just barly fit.
I suspect the last option you have may be a better design so that you
can have the 'extra' pdp 11 instructions decoded and later you can upgrade/test
the microcode.

> Richard
>


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On Wed, 2007-08-22 at 12:12 -0600, woodelf wrote:

> Also UNIX may require 1) a memory management unit 2) Floating point
> too.

1) yes
2) no

Hellwig



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> I used the other brand of FPGA's and was doing my logic design as
schematic
> entry. I had 750 CLB's and 256x32 ram so I configured the random logic
> to fit in the ram to save space. This was a compile time option.
> Even so the routing is what killed the project. It just barly fit.
> I suspect the last option you have may be a better design so that you
> can have the 'extra' pdp 11 instructions decoded and later you can
upgrade/test
> the microcode.
>

According to the Spartan 3 datasheet, your device (based on CLBs)
would be equivalent to 400k gates which would be a XC3S400 and this
Xilinx FPGA would have 56k bits of distributed RAM and 288k bits of
BlockRAM.

The XC3S1000 (the 1M gate version on the Spartan 3 Starter Board)
would have 1920 CLBs, 120k bits of distributed RAM and 432k bits of
BlockRAM along with 24 hardware multipliers.

The starter board includes 1MB of asynchronous RAM which should be
more than enough for the PDP-11/40.

I like the idea of a $149 PDP-11/40 running Unix. Now if I can just
port the code.

Richard



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rtstofer wrote:

> The starter board includes 1MB of asynchronous RAM which should be
> more than enough for the PDP-11/40.

The new boards are nice but since I am doing homebrew at home
I am rather limited with my limited construction skills.

Does the board have a provision for a serial rom for power up
FPGA load?

>
> I like the idea of a $149 PDP-11/40 running Unix. Now if I can just
> port the code.

You need another meg ... REAL UNIX is only 22 bit adressing. :(

> Richard



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On Wed, 2007-08-22 at 15:24 -0600, woodelf wrote:

> You need another meg ... REAL UNIX is only 22 bit adressing. :(

Not quite true. You can very reasonably run
UNIX 7th Edition within 256 kB of RAM.

Hellwig



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> The new boards are nice but since I am doing homebrew at home
> I am rather limited with my limited construction skills.
I have the same problem - I can't handle BGA devices and I am
reluctant to solder 208 pin flat packs.
>
> Does the board have a provision for a serial rom for power up
> FPGA load?
Absolutely!
>
> >
> > I like the idea of a $149 PDP-11/40 running Unix. Now if I can just
> > port the code.
>
> You need another meg ... REAL UNIX is only 22 bit adressing. :(
Not a problem! The Spartan 3E Starter Board (different board) has 32
MB DDR SDRAM but only 500k gates. It also has an Ethernet chip and
some other goodies for the same price. There is a MONSTER 1.6M gate
Spartan 3E Development Board with some neat features for $295 (out of
my price range for this project).

Or the NEXYS board with 1M gate device for $119 which has 16 MB of
PSDRAM. This is certainly viable!

It looks like the author only used an 18 bit address but I'm not 100%
sure of that.

Richard



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--- In f...@yahoogroups.com, Hellwig Geisse
wrote:
>
> On Wed, 2007-08-22 at 15:24 -0600, woodelf wrote:
>
> > You need another meg ... REAL UNIX is only 22 bit adressing. :(
>
> Not quite true. You can very reasonably run
> UNIX 7th Edition within 256 kB of RAM.
>
> Hellwig
>

Would that also apply to Unix V6? As I look at the memory address
lines, I only see 0..17 or 256 kB.

Richard



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An Altera board that seems more than adequate would be the Cyclone II
FPGA Starter Development Kit. At $150 is is reasonable and has 8 MB
of SDRAM as well as 32KB of SRAM and 4 MB Flash. It has a lot of
gadgets (audio CODEC, 10 switches, 4 pushbuttons, 18 LEDs and 4 ea 7
segment display) but the best part is that it has two 40 pin expansion
ports with 36 signals each. With a little cable juxtaposition, one of
these would drive an ATA drive quite nicely.

Or, skip the ATA thing and use the on-board SD/MMC socket.

I haven't used Altera but I am certainly thinking about this board
http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html

Richard



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On Wed, 22 Aug 2007 23:32:41 -0000, you wrote:

>--- In f...@yahoogroups.com, Hellwig Geisse
>wrote:
>>
>> On Wed, 2007-08-22 at 15:24 -0600, woodelf wrote:
>>
>> > You need another meg ... REAL UNIX is only 22 bit adressing. :(
>>
>> Not quite true. You can very reasonably run
>> UNIX 7th Edition within 256 kB of RAM.
>>
>> Hellwig
>
>Would that also apply to Unix V6? As I look at the memory address
>lines, I only see 0..17 or 256 kB.
>
>Richard

My recollection of v6 (1977-'78 when I last went over the code in
detail [may still have a listing around here]) is that 256k was more
than enough memory for good use. I think it was released earlier
(1976 or so?) Anyway, it was in going through the O/S listings of V6
that I first learned C. (I already knew PDP-11 assembly well, by
then.)

By the way, I like the idea of an FPGA-based PDP-11/40 (or better, a
PDP-11/70 with its cache memory) with a full front panel that usually
appeared with them. (I did not ENJOY the ones without the array of
address/data switches on their front panels, such as the PDP-11/24,
PDP-11/34 or the PDP-11/44.)

Jon



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woodelf wrote:
> You need another meg ... REAL UNIX is only 22 bit adressing. :(

Many versions of Unix, including 6th edition and 7th edition, ran fine on
a PDP-11 with only 18-bit addressing. Good thing, too, as the early
PDP-11s didn't have 22-bit addressing. Unix commonly ran on the 11/40,
11/45, and 11/34, all of which only had 18-bit addressing.

22-bit addressing and separate I/D space are only required for later
versions such as 2.11 BSD. 22-bit addressing is only available on
the 11/44, 11/70, and F11 and J11 based systems.

Eric


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Ya i grabbed a copy too, while it was there.

Curious tho, what is the small board in that last picture, with the HDD=20
attached?

>
> Re: POP-11 (PDP-11/40 in an FPGA)
> Posted by: "rtstofer" r...@pacbell.net =A0 rtstofer
> Tue Aug=A021,=A02007 5:02=A0pm (PST)
> It's back! See http://shimizu-lab.dt.u-tokai.ac.jp/pop11.html
>
> This time I'll download it and put it on a CD! Perhaps this winter
> I'll get around to converting it to run on a Spartan 3 Starter Board.
> If I read the info correctly, it was built on a chip with 100k gates
> so a 1M gate Spartan 3 ought to work!
>
> Richard
To post a message, send it to: f...@yahoogroups.com
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om=20

=20


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> Many versions of Unix, including 6th edition and 7th edition, ran
fine on
> a PDP-11 with only 18-bit addressing.

In which case the Spartan 3 Starter Board with 1 MB of asynchronous
RAM is adequate.

The only 'gotcha' I can see is the fact that the Spartan 3 FPGA is not
5V tolerant and the hard disk is 5V logic. There are level shifters
to deal with this. The A2 connector has plenty of signals (31 that I
have been able to use) for the hard drive. A little interface board
that plugs into A2, performs level shifting and provides a header for
the 40 pin IDE cable would be perfect.

There's plenty of space on the B1 connector to do the SPI <-> Panel stuff.

I'll get started as soon as the weather changes. Summer is for boats,
winter is for electronics.

Richard



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Hi Richard,

> The only 'gotcha' I can see is the fact that the Spartan
> 3 FPGA is not 5V tolerant and the hard disk is 5V logic.
> There are level shifters to deal with this.

Spartan-3/-3E I/O can be made 5V-tolerant by using an external series
current limiting resistor to limit the current into the upper clamp diode to
10 mA. This makes the input 5V-tolerant. If the I/O is TTL, which it
probably is, you can drive it with a CMOS output, and the swing will be TTL
compliant, which is a low below .8V and a high above 2V.

Regards,

Austin


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Hellwig Geisse wrote:
> On Wed, 2007-08-22 at 15:24 -0600, woodelf wrote:
>
> > You need another meg ... REAL UNIX is only 22 bit adressing. :(
>
> Not quite true. You can very reasonably run
> UNIX 7th Edition within 256 kB of RAM.
>
> Hellwig
I forgot -- UNIX came before Bill Gates and 640K of memory.
Unix does cheat however, most of the people back then time sharing
tended only to use small sized programs rather than the monster sized
programs of today.
I/O I expect was often 300 baud too.
Ben alias woddelf


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I am delighted in this interest in FPGA pdp-11s. I hope you folks have a
blast. I am going to build one from scratch some day when I have the time.

I wonder if there is slightly more verisimilitude in an FPGA
reimplementation if one goes to the effort of buliding a datapath adapted
from original processor schematics.
Anyway, thanks to the great directions of Jonathan Engdahl
http://home.alltel.net/engdahl/PDP-11_53.htm about five years ago I
converted a KDJ11 to a 'pdp-11/53', with an integrated 1.5 MB of RAM, clock,
serial, etc., put it in an old MicroVax QBUS chassis with a DEQNA (?)
network card and a CMD QBUS (T)MSCP SCSI controller and a few other things.
It runs 2.11 BSD.

I think I had better power it up again before I forget entirely how to do
so.

In my garage awaits a treasure, an actual pdp-11/45, a grotty looking RK05,
and a DecWriter. It is not the 11 that I learned Unix on (Waterloo Math UNIX
(modified v6) in 1979 in MC6098A) but is one of its sister machines, CCNG A
or D, from the Waterloo Electrical Engineering department's Computer
Communications Network Group, from Waterloo, to Bellevue, WA, by way of
South Carolina. It is pictured here, prior to arriving in my garage:
http://www.woffordwitch.com/PDP1145.asp. I cannot just plug it in and see
what happens. Rather I am going to have to learn about reconditioning old
power supplies and so forth. Someday!

Happy hacking,
Jan.


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--- In f...@yahoogroups.com, "Austin Franklin"
wrote:
>
> Hi Richard,
>
> > The only 'gotcha' I can see is the fact that the Spartan
> > 3 FPGA is not 5V tolerant and the hard disk is 5V logic.
> > There are level shifters to deal with this.
>
> Spartan-3/-3E I/O can be made 5V-tolerant by using an external series
> current limiting resistor to limit the current into the upper clamp
diode to
> 10 mA. This makes the input 5V-tolerant. If the I/O is TTL, which it
> probably is, you can drive it with a CMOS output, and the swing will
be TTL
> compliant, which is a low below .8V and a high above 2V.
>
> Regards,
>
> Austin
>

I know this was the case for the Spartan IIE where a simple 100 ohm
resistor was sufficient to protect the inputs. However, Xilinx stated
that this resistor/tolerant solution would work on the IIE.

I haven't been able to find any Xilinx documentation suggesting that
the resistor solution would work on the Spartan 3.

I do see where Digilent used 270 ohm resistors on the Keyboard PS2
inputs because they do allow the keyboard to be driven with either 5V
or 3.3V from the S3 board. So, it must work!

I'll keep reading - it has to be there somewhere.

Richard



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On Wed, 2007-08-22 at 23:44 +0000, rtstofer wrote:
> An Altera board that seems more than adequate would be the Cyclone II
> FPGA Starter Development Kit. At $150 is is reasonable and has 8 MB
> of SDRAM as well as 32KB of SRAM and 4 MB Flash. It has a lot of
> gadgets (audio CODEC, 10 switches, 4 pushbuttons, 18 LEDs and 4 ea 7
> segment display) but the best part is that it has two 40 pin expansion
> ports with 36 signals each. With a little cable juxtaposition, one of
> these would drive an ATA drive quite nicely.

My favorite board, which I used to implement my 32-bit processor
on, is this one from XESS:
http://www.xess.com/prod039.php3
1M Spartan-3, 32 MByte SDRAM, 2 MByte Flash (holds FPGA bitstring
and resident ROM monitor for my system), keyboard port, VGA port,
parallel port, Ethernet, serial port, IDE interface, much more...

I'm in the process of porting UNIX 7th Edition to this system.
I choose V7 because it has a reasonably small code base. I would
have chosen V6, but the C syntax is (nowadays) non-standard and,
more important, the context switch mechanism is not portable,
as Dennis Ritchie explained:
http://www.cs.bell-labs.com/who/dmr/odd.html
This was corrected in V7.

Hellwig


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Austin wrote:
> Spartan-3/-3E I/O can be made 5V-tolerant by using an external series
> current limiting resistor to limit the current into the upper clamp diode
> to
> 10 mA. This makes the input 5V-tolerant. If the I/O is TTL, which it
> probably is,

If you're talking about the ATA disk, or a CF card, they are specified
at TTL input thresholds, but are usually implemented with CMOS logic,
so any outputs from the disk or card will swing close to the rail.
Series resistors might be adequate for old, slow ATA modes, but will
likely not work if you try to do the faster DMA modes.

Eric


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woodelf wrote:
> Unix does cheat however, most of the people back then time sharing
> tended only to use small sized programs rather than the monster sized
> programs of today.

Writing compact, efficient code is cheating?

> I/O I expect was often 300 baud too.

If you were using a DECwriter or the like. If you used a Teletype,
it was 110. If you used a glass TTY, it might have been 9600.

Eric


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Hi Hellwig, etal

I also have an XESS XSA-3S1000 and XST3.0 which I bought for another PDP
project. The XST 3.0 board has an IDE disk interface, but to the best of
my knowledge does not use series limit resisters. When I queried Dave
Vanden Bout from Xess about this, he said, and I quote:

"Most modern disks use 3.3V signals (actually LVTTL) on their IDE
interfaces, so there is no problem with the XSA board. You should
connect the IDE to CF adapters to use 3.3V."

I'm not sure what constitutes a "modern" disk drive, but it might be
worth testing the signals with a multimeter first. I was asking about
connecting Compact Flash which is why the CF reference. You must run CF
off a 3.3V rail, even though the CF to IDE adapters I bought have a
standard 3.5" floppy power connector on them.

If you want to interface an IDE drive to the Digilent Spartan 3 starter
board, a friend suggested using the Digilent Test Point Header 1 board
which has a male and female 2 x 20 pin connector which I believe allows
you to jumper the appropriate signals to the IDE pins.

An example is shown here:
http://www.mirrow.com/FPGApple/

Hi to Alex if you are on the list.

By the way ... thanks for the links Hellwig.

I found my way to St. Brian Kernigan's web site which was very
interesting. I must admit I expected something a little grander. But it
did have a few interesting tricks with PDP11 assembler code :-)

John.

Hellwig Geisse wrote:
>
> My favorite board, which I used to implement my 32-bit processor
> on, is this one from XESS:
> http://www.xess.com/prod039.php3
> 1M Spartan-3, 32 MByte SDRAM, 2 MByte Flash (holds FPGA bitstring
> and resident ROM monitor for my system), keyboard port, VGA port,
> parallel port, Ethernet, serial port, IDE interface, much more...
>
> I'm in the process of porting UNIX 7th Edition to this system.
> I choose V7 because it has a reasonably small code base. I would
> have chosen V6, but the C syntax is (nowadays) non-standard and,
> more important, the context switch mechanism is not portable,
> as Dennis Ritchie explained:
> http://www.cs.bell-labs.com/who/dmr/odd.html
>
> This was corrected in V7.
>
> Hellwig
>
>
>
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent


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> When I queried Dave
> Vanden Bout from Xess about this, he said, and I quote:
>
> "Most modern disks use 3.3V signals (actually LVTTL) on their IDE
> interfaces, so there is no problem with the XSA board. You should
> connect the IDE to CF adapters to use 3.3V."

I have no idea what he said in that quote! There is more info at the
XESS site. The BurchEd IDE interface board for the Spartan IIE was
just a collection of resistors (100 ohms, I believe). It was
compatible with a HD or CF running on 5V (this is legal).

>
> If you want to interface an IDE drive to the Digilent Spartan 3 starter
> board, a friend suggested using the Digilent Test Point Header 1 board
> which has a male and female 2 x 20 pin connector which I believe allows
> you to jumper the appropriate signals to the IDE pins.

No such luck! The board has a male end connector and a female end
connector to allow it to be placed between the main board and other
gadgets plus a header in the middle. It is wired straight through.

I'm giving more consideration to the Altera board. It has 315 user
I/O which is more than the total pin count for the Spartan 3. Having
an extra 36 signal header makes it easy to connect a logic analyzer
while still having room for the CF/HDD.

I think I will use a CF device. It's not like this machine will get a
lot of use and I KNOW the CF device is 3.3V. OTOH, I wonder if the
swap partition will be overused (V6 does use swap, right?).

There is a draft of the 2008 ATA spec here:
http://t13.org/Documents/UploadedDocuments/project/d2008r7b-ATA-3.pdf
It appears that the output high voltage is at least 2.5V with a load
of 400 uA. It accepts an input high voltage of 2.0V. Given the
limited source current, I would think the resistors would work fine.
I might not choose to do it that way but I think it will work.

Richard



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On Thu, 2007-08-23 at 15:36 +0000, rtstofer wrote:

> I'm giving more consideration to the Altera board. It has 315 user
> I/O which is more than the total pin count for the Spartan 3. Having
> an extra 36 signal header makes it easy to connect a logic analyzer
> while still having room for the CF/HDD.

During the development of my CPU I had the problem that simulations
with Icarus Verilog and the actual implementation in the FPGA gave
different results. As I have no logic analyzer, I came up with the
following trick, which undoubtedly others have employed as well:
implement a bare-bones logic analyzer within the FPGA using block
RAM to catch the signals. When the buffer is full, read it out over
the serial line and display the results on a PC.

> I think I will use a CF device. It's not like this machine will get a
> lot of use and I KNOW the CF device is 3.3V. OTOH, I wonder if the
> swap partition will be overused (V6 does use swap, right?).

Yes, V6 does swapping.

Hellwig



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> During the development of my CPU I had the problem that simulations
> with Icarus Verilog and the actual implementation in the FPGA gave
> different results. As I have no logic analyzer, I came up with the
> following trick, which undoubtedly others have employed as well:
> implement a bare-bones logic analyzer within the FPGA using block
> RAM to catch the signals. When the buffer is full, read it out over
> the serial line and display the results on a PC.

Or, grab a spare Spartan 3 Starter Board and visit
http://www.sump.org/projects/analyzer/ I had a 200k gate version that
was undersized for my project but more than adequate for the logic
analyzer.

I like your idea of using BlockRAM. On my recent project, I didn't
have BlockRAM left over but for the POP11 I don't think BlockRAM will
be used at all. It might be cool to modify the sump.org project to
put the logic analyzer inside the FPGA permanently. There's plenty of
space. Maybe define a separate USART and connect an RS232 dongle.
Sample size will be limited by the size of BlockRAM or, on the Altera
board, use the 512KB of SRAM. That still leaves the 8 MB of SDRAM for
the POP-11 - although interfacing SDRAM to the POP-11 is much more
difficult than SRAM.

I REALLY like your idea!

Richard



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FWIW, the POP-11 code doesn't appear to handle a front panel. For a
first cut, that is probably ok but I really want the blinking lights
and switches. I might settle for 7 segment displays (in octal, of
course).

Anyone have a source for paddle handle toggle switches? Ok, now are
they reasonably priced?

Richard



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John Kent wrote:

Well I still live in 5 volt logic land!
So are the drives I buy ( for now or have kicking around ).
I suspect for real PDP-11 style I/O the IDE interface would
use DMA so that would be external to the FPGA.

> I also have an XESS XSA-3S1000 and XST3.0 which I bought for another PDP
> project. The XST 3.0 board has an IDE disk interface, but to the best of
> my knowledge does not use series limit resisters. When I queried Dave
> Vanden Bout from Xess about this, he said, and I quote:

I think they make CPLD's that have 5 volt I/O & 3.3 I/O. If so that
would be the cat's meyow.

> I'm not sure what constitutes a "modern" disk drive, but it might be
> worth testing the signals with a multimeter first. I was asking about
> connecting Compact Flash which is why the CF reference. You must run CF
> off a 3.3V rail, even though the CF to IDE adapters I bought have a
> standard 3.5" floppy power connector on them.

Why not just go USB ... everything else is that now?


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rtstofer wrote:
> FWIW, the POP-11 code doesn't appear to handle a front panel. For a
> first cut, that is probably ok but I really want the blinking lights
> and switches. I might settle for 7 segment displays (in octal, of
> course).
>
> Anyone have a source for paddle handle toggle switches? Ok, now are
> they reasonably priced?
>
> Richard

Ack! Cough Cough Cough. You can get Surplus paddle switches cheap
but not matching momentary contact ones.
http://www.imsai.net/parts/parts.htm



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On Thu, 2007-08-23 at 16:35 +0000, rtstofer wrote:

> Or, grab a spare Spartan 3 Starter Board and visit
> http://www.sump.org/projects/analyzer/ I had a 200k gate version that
> was undersized for my project but more than adequate for the logic
> analyzer.

Thanks for the link. My analyzer works very similar, has
more channels (128) but is less deep (512 samples), and has
only a simple trigger. And I never had the time to write
viewing software other than a hexadecimal listing... ;-)

> I REALLY like your idea!

If anyone is interested, I will make the code available.

Hellwig


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--- In f...@yahoogroups.com, woodelf wrote:
>
> rtstofer wrote:
> >
> >
> > FWIW, the POP-11 code doesn't appear to handle a front panel. For a
> > first cut, that is probably ok but I really want the blinking lights
> > and switches. I might settle for 7 segment displays (in octal, of
> > course).
> >
> > Anyone have a source for paddle handle toggle switches? Ok, now are
> > they reasonably priced?
> >
> > Richard
>
> Ack! Cough Cough Cough. You can get Surplus paddle switches cheap
> but not matching momentary contact ones.
> http://www.imsai.net/parts/parts.htm
>

So, they're not reasonably priced. First there is the issue that
POP11 doesn't include front panel logic. Second, if I get the basic
processor to function I can build a first approximation using regular
toggle switches. Finally, if I REALLY like the machine and decide to
package it, I can part with a little money.

But there's a lot to do between now and then.

Richard



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Richard wrote:
> Anyone have a source for paddle handle toggle switches? Ok, now are
> they reasonably priced?

DEC made their own paddles, and I haven't seen anything close available
as a standard product.

The ones that were used on the IMSAI microcomputer are still available.
They cost about $10.50-12.00 each here, or $185 for the complete set of
22 used in the IMSAI:
http://www.imsai.net/parts/parts.htm

If you're buying a bunch of them, you can probably get a better deal
through a C&K (ITT Cannon) distributor. I haven't purchased any myself,
but as of 1997, Tim Shoppa reported that they were still available as part
number 7101-J4-Z-Q-E for on-on, and 7105-J4-Z-Q-E for momentary-off-
momentary. They were available in various colors, though only black,
red, and white were standard.

The latest data sheet doesn't show the J4 actuator, but there are some
others that might be suitable:

http://www.ittcannon.com/media/pdf/catalogs/Leaf/SW_rocker_7000.pdf

Eric


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--- In f...@yahoogroups.com, Hellwig Geisse
wrote:
>
> On Thu, 2007-08-23 at 16:35 +0000, rtstofer wrote:
>
> > Or, grab a spare Spartan 3 Starter Board and visit
> > http://www.sump.org/projects/analyzer/ I had a 200k gate version that
> > was undersized for my project but more than adequate for the logic
> > analyzer.
>
> Thanks for the link. My analyzer works very similar, has
> more channels (128) but is less deep (512 samples), and has
> only a simple trigger. And I never had the time to write
> viewing software other than a hexadecimal listing... ;-)
>
> > I REALLY like your idea!
>
> If anyone is interested, I will make the code available.
>
> Hellwig
>

Absolutely! I am getting jazzed about building this retro project.

I think your idea of limited samples is correct. I have no idea what
to do with 32k samples. If the problem takes that long to identify
itself I'll never solve it. Or, I'm looking in the wrong place.

There is also the advantage of having the samples sychronized to the
main clock. There is no need to oversample and this makes
interpretation easier.

A simple trigger is fine because there is no practical limit to the
logic that creates it.

I have a rather crude logic analyzer based on a BurchEd Spartan 2E
board for which I wrote a little Visual Basic display. Porting this
will be a lot easier than dealing with the sump.org project although
it is the superior analyzer.

Richard



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On Thu, 23 Aug 2007 11:02:45 -0600, you wrote:

>rtstofer wrote:
>> FWIW, the POP-11 code doesn't appear to handle a front panel. For a
>> first cut, that is probably ok but I really want the blinking lights
>> and switches. I might settle for 7 segment displays (in octal, of
>> course).
>>
>> Anyone have a source for paddle handle toggle switches? Ok, now are
>> they reasonably priced?
>>
>> Richard
>
>Ack! Cough Cough Cough. You can get Surplus paddle switches cheap
>but not matching momentary contact ones.
>http://www.imsai.net/parts/parts.htm

Thanks for the link! It turns out that I bought a whole bunch of the
IMSAI switches back around 1979 or so (I loved them a LOT more than my
silly metal-handled Altair 8800 switches on the unit I'd built.) Still
have them. They are worth over US$11 now??!! Wow!! I am rich!
Probably have several thousand dollars worth of them, today.

Jon



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Jonathan Kirwan wrote:

> Thanks for the link! It turns out that I bought a whole bunch of the
> IMSAI switches back around 1979 or so (I loved them a LOT more than my
> silly metal-handled Altair 8800 switches on the unit I'd built.) Still
> have them. They are worth over US$11 now??!! Wow!! I am rich!
> Probably have several thousand dollars worth of them, today.

Got any to sell cheap?
> Jon


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On Thu, 23 Aug 2007 14:05:11 -0600, you wrote:

>Jonathan Kirwan wrote:
>
>> Thanks for the link! It turns out that I bought a whole bunch of the
>> IMSAI switches back around 1979 or so (I loved them a LOT more than my
>> silly metal-handled Altair 8800 switches on the unit I'd built.) Still
>> have them. They are worth over US$11 now??!! Wow!! I am rich!
>> Probably have several thousand dollars worth of them, today.
>
>Got any to sell cheap?
>> Jon

Hehe. I'll first have to go into my 1200 sw ft, 35' ceiling shed and
look through decades of interesting accumulations for the brown paper
sacks in which I kept them. Think about the end of the movie,
"Raiders of the Lost Ark," here. ;) I suppose it would be worth some
trouble for a good cause, though.

Probably my favorite front panel style was the type used on the front
panel of the HP2116 processor. Soft, 2cm square from memory,
incandescent lighted translucent (avoided the need for separate lights
to indicate bit values), toggle on, toggle off, push buttons.

I also enjoyed the PDP-11 front panel switches and got fairly quick at
them. I think I still liked the HP ones better, but these were fine.

Of course, I also used the Altair 8800 (hardens your finger tips like
playing a guitar may, because of the metal bats) a lot but didn't
enjoy it nearly as much as the IMSAI 8080. Which is why I bought a
bunch of the switches at the time, thinking about replacing my Altair
switches with them and having a bunch left over for whatever came up.
Never did do it, though. So the switches just sat around.

Someone told me, a few years back, that getting a high pressure
plastic molds done in China isn't too expensive (I used to do
apprentice-type work in a shop that made them and got really bored
doing diamond dust polishing!) Should be possible to get a line of
good switches going for not too much investment that way. With those
IMSAI switches supposedly selling at those prices, I have to imagine
that there might be enough commerce to make a go of it making either
exact duplicates (ready replacement market, apparently) or separately
for some even better use on a new front panel design.

Jon



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Jonathan Kirwan wrote:

> Hehe. I'll first have to go into my 1200 sw ft, 35' ceiling shed and
> look through decades of interesting accumulations for the brown paper
> sacks in which I kept them. Think about the end of the movie,
> "Raiders of the Lost Ark," here. ;) I suppose it would be worth some
> trouble for a good cause, though.

So what else do you have for sale?
> Someone told me, a few years back, that getting a high pressure
> plastic molds done in China isn't too expensive (I used to do
> apprentice-type work in a shop that made them and got really bored
> doing diamond dust polishing!) Should be possible to get a line of
> good switches going for not too much investment that way. With those
> IMSAI switches supposedly selling at those prices, I have to imagine
> that there might be enough commerce to make a go of it making either
> exact duplicates (ready replacement market, apparently) or separately
> for some even better use on a new front panel design.

Since DEC stopped making switches there is a small amount of people
looking to have replacement handles at least for front panels.
Any idea of prices for a lot of say 250 switch handles?

> Jon


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Mouser carries the NKK series of Rocker/Paddle switches and the prices
seem reasonable ($4 to $7). I haven't checked size or any other info.

An example: http://www.mouser.com/search/refine.aspx?Ntt=633-M201201E

Richard



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On Thu, 2007-08-23 at 17:18 +0000, rtstofer wrote:

> Absolutely! I am getting jazzed about building this retro project.

Ok folks, as promised, here it is:

http://homepages.fh-giessen.de/~hg53/LogiProbe

I quickly hacked a page of instructions how to use the beast,
something that I never got to when actually working with it... ;-)

If you have questions, feel free to ask.

Regards,
Hellwig



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Hi Richard ...

Sorry ... I'm a bit behind on the traffic.
Is there some way of removing all this HTML grunge that comes with the
yahoo posts ?

My understanding of what Dave was saying was that the drives these days
must use 3.3V I/O chips on the IDE bus. 3.3V logic is high enough to
overcome the 5V TTL logic threshold and provided the 3.3 V inputs are 5V
tolerant, there should be no problem connecting them to a 5V bus. I am
told that even printer ports these days often run at 3.3V.

I have noted the 100 ohm resistors on the B5-X300 IDE interface board
(not that I have one). I think Tony might even use them on the
peripheral interconnect board. so you can run that at 5V. The B5-X300 is
a Spartan 2E and the question was raised whether you could do the same
trick on the Spartan 3, and I suspect you can, because the Spartan 3
starter kit can interface to a 5V PS/2 keyboard, and I don't seem to
have blown my board up doing so. I'd imagine that the Spartan 3, like
most chips these days, have reversed bias clamp protection diodes on the
inputrs, so provided you don't put too much current through the diode,
you should be fine. (I'm not liable if it blows your chip up through !).

OK on the connector on the Spartan 3 starter board being female. I must
admit I had forgotten about that. I guess they needed to guard the pins
for shorts and a female connector provides more protection for that. You
can actually get male IDC ribbon connectors. I have a few. Obviously
what they did on the Apple project was to plug the CF to IDE adapter,
which had a male connector on it, directly into the Test Point Header.

Nobody picked me up on Brian Kernigan rather than Dennis Ritchie.

John.
rtstofer wrote:
> > When I queried Dave
> > Vanden Bout from Xess about this, he said, and I quote:
> >
> > "Most modern disks use 3.3V signals (actually LVTTL) on their IDE
> > interfaces, so there is no problem with the XSA board. You should
> > connect the IDE to CF adapters to use 3.3V."
>
> I have no idea what he said in that quote! There is more info at the
> XESS site. The BurchEd IDE interface board for the Spartan IIE was
> just a collection of resistors (100 ohms, I believe). It was
> compatible with a HD or CF running on 5V (this is legal).
> >
> > If you want to interface an IDE drive to the Digilent Spartan 3 starter
> > board, a friend suggested using the Digilent Test Point Header 1 board
> > which has a male and female 2 x 20 pin connector which I believe allows
> > you to jumper the appropriate signals to the IDE pins.
>
> No such luck! The board has a male end connector and a female end
> connector to allow it to be placed between the main board and other
> gadgets plus a header in the middle. It is wired straight through.
> __.
-- http://www.johnkent.com.au
http://members.optushome.com.au/jekent


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--- In f...@yahoogroups.com, Hellwig Geisse
wrote:
>
> On Thu, 2007-08-23 at 17:18 +0000, rtstofer wrote:
>
> > Absolutely! I am getting jazzed about building this retro project.
>
> Ok folks, as promised, here it is:
>
> http://homepages.fh-giessen.de/~hg53/LogiProbe
>
> I quickly hacked a page of instructions how to use the beast,
> something that I never got to when actually working with it... ;-)
>
> If you have questions, feel free to ask.
>
> Regards,
> Hellwig
>

Very nice! Thanks for posting it.

I'm going to start a new thread re: free tools. I didn't know that
there were free simulators and graphic wave viewers.

Richard



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> I have noted the 100 ohm resistors on the B5-X300 IDE interface board
> (not that I have one). I think Tony might even use them on the
> peripheral interconnect board. so you can run that at 5V. The
B5-X300 is
> a Spartan 2E and the question was raised whether you could do the same
> trick on the Spartan 3, and I suspect you can, because the Spartan 3
> starter kit can interface to a 5V PS/2 keyboard, and I don't seem to
> have blown my board up doing so. I'd imagine that the Spartan 3, like
> most chips these days, have reversed bias clamp protection diodes on
the
> inputrs, so provided you don't put too much current through the diode,
> you should be fine. (I'm not liable if it blows your chip up through !).

Agreed. However, the Xilinx documentation for the Spartan 2E (only)
describes using the series resistors and claims the IO lines are 5V
tolerant when the resistors are used. There is no similar statement
for either the Spartan 2 or the Spartan 3 devices.

I don't doubt that resistors work because the Starter Board uses them
for the keyboard input. The keyboard voltage can be jumper selected
to be either 3.3V or 5V.

Where I get concerned is when there are MANY pins with series
resistors dumping current through the diodes. I don't know if the
heating will be a factor. Increasing the value of the resistors to
reduce current does nothing to improve the signal.

The problem is: I don't know and Xilinx isn't telling.

I would probably build a small PCB to connect between the A2 port and
the IDE cable. This would allow me to unscramble signal lines and
change the orientation/gender of the cable<->board connection.

Given that I build such a board, do I populate it with resistors or
level translators? Since the difference in cost is negligible, I'll
choose the translators. At the moment, I am considering the TI
74LVT16245A device: http://www.ti.com/lit/gpn/sn74lvt16245a but there
are others.

Richard



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> the question was raised whether you could do the same trick
[series resistors for 5V tolerance]
> on the Spartan 3, and I suspect you can, [...] I'd imagine that the
> Spartan 3, like most chips these days, have reversed bias clamp
> protection diodes on the inputrs

It's not something that one has to suspect or imagine; a Google search
for "Xilinx Spartan-3 5V" reveals that it is documented in Xilinx
Answer Record 19146:

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19146

Eric


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On Sat, 2007-08-25 at 13:52 +0000, rtstofer wrote:
> Re: the built-in logic analyzer. I was looking at GTKWave and it
> accepts VCD files for input. It assumes they come from a simulator
> but I figure that if I can create a compatible file from the logic
> analyzer dump, GTKWave won't know the difference.
>
> Then I ran across la2vcd, a conversion program from a logic analyzer
> dump file to VCD.

I once wrote such a program as part of a project in which
I created my own hardware description language (named SHLD,
"simple hardware description language") and a simulator for
it. I wanted to display its output nicely and so wrote a
converter from the output of my simulator to VCD format.
You can grab the whole project from here:
http://homepages.fh-giessen.de/~hg53/shdl
The converter can be found in subdirectory vcd.

> In the sump.org Logic Analyzer, he uses the buffer memory in different
> widths/depths. For the Spartan 3 1M gate version, we have 432k bits
> of BlockRam. Assuming no other use for this, it could hold 3456
> samples of 128 bit width or 13,824 samples of 32 bit width, etc. The
> console application sends commands to the LA to select things like
> trigger condition, width/depth, etc. Maybe it is worth the effort to
> port that LA to an embedded module.

Most projects implemented in Spartan 3 will have good use for
the block RAM within the projects themselves. So I don't think
it's a good idea to reserve all of the RAM for the analyzer.

Hellwig


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On Thu, 2007-08-23 at 17:18 +0000, rtstofer wrote:
> --- In f...@yahoogroups.com, Hellwig Geisse wrote:
> > If anyone is interested, I will make the code available.
>
> Absolutely! I am getting jazzed about building this retro project.

Ok folks, as promised, here it is:

http://homepages.fh-giessen.de/~hg53/LogiProbe

I quickly hacked a page of instructions how to use the beast,
something that I never got to when actually working with it... ;-)

If you have questions, feel free to ask.

Regards,
Hellwig


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On Sat, 2007-08-25 at 13:52 +0000, rtstofer wrote:
> Re: the built-in logic analyzer. I was looking at GTKWave and it
> accepts VCD files for input. It assumes they come from a simulator
> but I figure that if I can create a compatible file from the logic
> analyzer dump, GTKWave won't know the difference.
>
> Then I ran across la2vcd, a conversion program from a logic analyzer
> dump file to VCD.

I once wrote such a program as part of a project in which
I created my own hardware description language (named SHLD,
"simple hardware description language") and a simulator for
it. I wanted to display its output nicely and so wrote a
converter from the output of my simulator to VCD format.
You can grab the whole project from here:
http://homepages.fh-giessen.de/~hg53/shdl
The converter can be found in subdirectory vcd.

> In the sump.org Logic Analyzer, he uses the buffer memory in different
> widths/depths. For the Spartan 3 1M gate version, we have 432k bits
> of BlockRam. Assuming no other use for this, it could hold 3456
> samples of 128 bit width or 13,824 samples of 32 bit width, etc. The
> console application sends commands to the LA to select things like
> trigger condition, width/depth, etc. Maybe it is worth the effort to
> port that LA to an embedded module.

Most projects implemented in Spartan 3 will have good use for
the block RAM within the projects themselves. So I don't think
it's a good idea to reserve all of the RAM for the analyzer.

Hellwig



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> It's not something that one has to suspect or imagine; a Google search
> for "Xilinx Spartan-3 5V" reveals that it is documented in Xilinx
> Answer Record 19146:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19146
>
> Eric
>

Thanks for the link, I had been searching Xilinx for that answer but
it was quite a while back.

I have decided for my current project to implement CF drives which
operate fine at 3.3V. For the POP-11 project I may do the same.
There is something satisfying about totally silent computers.

Richard



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> Most projects implemented in Spartan 3 will have good use for
> the block RAM within the projects themselves. So I don't think
> it's a good idea to reserve all of the RAM for the analyzer.
>
> Hellwig
>

Almost certainly true! However, for the POP-11 project, I haven't
seen much need for BlockRAM. In looking at the code, as given, I
don't see any internal RAM used other than what might be allocated
during synthesis.

Richard



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> I once wrote such a program as part of a project in which
> I created my own hardware description language (named SHLD,
> "simple hardware description language") and a simulator for
> it. I wanted to display its output nicely and so wrote a
> converter from the output of my simulator to VCD format.
> You can grab the whole project from here:
> http://homepages.fh-giessen.de/~hg53/shdl
> The converter can be found in subdirectory vcd.

Looking at the SFL code for the POP-11/40 project, I have to say that
the SFL language is the most descriptive I have ever seen. It is
certainly a 'high level' approach to hardware description, far removed
from RTL.

What I'm not as keen on is the fact that the translation to VHDL
creates a lot of subexpressions which get 'v_netxxx' (or similar)
names. It is sometimes difficult to figure out just what is happening.

I started looking at the idea of taking the translated VHDL and
recoding it so that I can understand what is going on. I have made
some progress (the top module and the ALU) but I am beginning to think
it is a fools' exercise. If I could really understand SFL, what
difference does it make if the VHDL is a little obscure?

The POP-11 is still a backburner project. I have purchased a few used
books re: the PDP-11 but it will be a while before I get deeply involved.

Richard



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Chuck wrote:
> There are copyrights on the MICROCODE which was the basis for most if
> not all of the LSI-11 variants of the machine. Those copyrights are
> still valid (75 years post partum)

Are you sure the microcode is copyrighted? In the US, works created before
March 1, 1989 (effective date of the Berne Convention Implementation Act
of 1988, U.S. Public Law 100-568) had to bear a copyright notice in order
to be copyrighted. See 17 U.S.C. 405(a).

There are limited exceptions that allowed the owner of a work to correct
an accidental omission of the copyright notice, but I don't think DEC
PDP-11 microcode qualifies under any of these exceptions.

There is also a way for a copyright that was "lost" under the Berne
Convention Implementation Act to be restored under certain conditions
(Uruguay Round Agreements Act of 1994, U.S. Public Law 103-465), but
I don't think the PDP-11 microcode qualifies under that exception either.

Eric


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Ok a couple of questions. I am not sure if this list is dead or not
but I'll see if I can add to the discussion.

The PDP 11 patents that DEC held are all expired (20 years) the last
one I believe expired in 2003 for some sort of PDP-11/70 MMU thing.
There are copyrights on the MICROCODE which was the basis for most if
not all of the LSI-11 variants of the machine. Those copyrights are
still valid (75 years post partum) but you can write your own
microcode and not worry too much. There is a company (whose name
escapes me) which used to make a pretty penny selling FPGA based
PDP-11s that ran faster than DEC ones and they were pretty aggressive
at pursuing people back in the 90's. Don't know if they are now or not.

Lastly the Altera DE2 board was clearly designed by someone who
thought building a PDP-11 was a cool idea since there are 18 switches,
LEDs and lots of peripherals on that board. And a decent sized FPGA. I
would expect you could boot RSX-11M, RT-11, Unix V7, or even RSTS/E on
that board while mimic'ing RL02's using FLASH ;-).

PLEASE PLEASE PLEASE post any VHDL you develop. The CPU test code
diagnostics are all available on line if you look around for the paper
tape images.

--Chuck



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Hi Chuck,

On Wed, 2007-09-19 at 06:56 +0000, Chuck McManis wrote:
> Ok a couple of questions. I am not sure if this list is dead or not
> but I'll see if I can add to the discussion.

the list is certainly not dead... ;-)

This particular thread was continued in private mail - we
doubted that anybody on the list was interested in a highly
specialized technical discussion. But we can of course continue
it here if there is interest.

> PLEASE PLEASE PLEASE post any VHDL you develop. The CPU test code
> diagnostics are all available on line if you look around for the paper
> tape images.

Do you have any pointers? I found
http://www.parse.com/~museum/pdp11/software/index.html
but I think there must be more, perhaps on bitsavers.

Hellwig


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On Thu, 27 Sep 2007 14:57:11 -0000, e2kcpu wrote:

>> This particular thread was continued in private mail - we
>> doubted that anybody on the list was interested in a highly
>> specialized technical discussion. But we can of course continue
>> it here if there is interest.
>
>Just continue here, as this list is not really busy, or high traffic ;-)
>And there are few people lurking on this list who know the pdp's
>pretty well ...

I'd agree, assuming those writing actively don't mind.

Jon
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> This particular thread was continued in private mail - we
> doubted that anybody on the list was interested in a highly
> specialized technical discussion. But we can of course continue
> it here if there is interest.

Just continue here, as this list is not really busy, or high traffic ;-)
And there are few people lurking on this list who know the pdp's
pretty well ...

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



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I am finally starting to work on this project. I used the sfl tools
to convert the sfl code to VHDL using the -split option. Now I am
looking at cleaning up the code.

In the segment_reg code, the converted VHDL has almost 700 lines of
code to implement two sets (kernel/user) of Page Address Registers and
Page Descriptor Registers.

Is there any reason I can't just declare a two-dimensional array of
std_logic_vectors? I'm thinking of something like:

entity segment_reg is port(
p_reset : in std_logic;
m_clock : in std_logic;
PDRout : out std_logic_vector(10 downto 0);
PARout : out std_logic_vector(11 downto 0);
PDRin : in std_logic_vector(10 downto 0);
PARin : in std_logic_vector(11 downto 0);
page : in std_logic_vector(2 downto 0);
mode : in std_logic;
writePDR : in std_logic;
writePAR : in std_logic;
seg_read : in std_logic);
end segment_reg;

architecture RTL of segment_reg is

type PAR_type is array (1 downto 0, 7 downto 0) of std_logic_vector(11
downto 0);
signal PARs : PAR_type := (others => (others => (others => '0')));

type PDR_type is array (1 downto 0, 7 downto 0) of std_logic_vector(10
downto 0);
signal PDRs : PDR_type := (others => (others => (others => '0')));

begin

process(m_clock, p_reset, mode, page)
begin
if m_clock'event and m_clock = '1' then
if p_reset = '1' then
PDRs <= (others => (others => (others => '0')));
PARs <= (others => (others => (others => '0')));
else
if writePDR = '1' then
PDRs(CONV_INTEGER(mode), CONV_INTEGER(page)) <= PDRin;
end if;
if writePAR = '1' then
PARs(CONV_INTEGER(mode), CONV_INTEGER(page)) <= PARin;
end if;
end if;
end if;
end process;

PDRout <= PDRs(CONV_INTEGER(mode), CONV_INTEGER(page)) when seg_read = '1'
else (others => '0');
PARout <= PARs(CONV_INTEGER(mode), CONV_INTEGER(page)) when seg_read = '1'
else (others => '0');

end RTL;

The WebPACK_ISE tools will compile the code and implement the design.
I was just wondering if I have made a huge error in simplifying the code.

Richard

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--- In f...@yahoogroups.com, "rtstofer" wrote:
>
> I am finally starting to work on this project. I used the sfl tools
> to convert the sfl code to VHDL using the -split option. Now I am
> looking at cleaning up the code.

I'm not sure that the best way to start ;-)
I would start from scratch.

> In the segment_reg code, the converted VHDL has almost 700 lines of
> code to implement two sets (kernel/user) of Page Address Registers and
> Page Descriptor Registers.
>
> Is there any reason I can't just declare a two-dimensional array of
> std_logic_vectors? I'm thinking of something like:

Normally, you could use a two-dimensional array for this.

> The WebPACK_ISE tools will compile the code and implement the design.

Which FPGA ? Could you post P&R reports ?

> I was just wondering if I have made a huge error in simplifying the
code.

do you have a good testbench ?

Cheers

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> I'm not sure that the best way to start ;-)
> I would start from scratch.

I think that is best. Since I can't find any decent hardware
reference manuals, I will probably use the SFL code as background
information.

>
> Which FPGA ? Could you post P&R reports ?

I will be using the Spartan 3 Starter Board
http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable
because it has the required memory and I already have three of them.
And it uses SRAM so I don't have to mess around with the interface.

I have already recoded the ALU. The propogation delay is horrible -
on the order of 33 nS or so. I'm going to take another look at it.
The Xilinx synthesizer is creating 26 logic levels! This is because