Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
See Also
Discussion Groups | FPGA-CPU | VHDL Implementation of xr16
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
VHDL Implementation of xr16 - Christian Plessl - Mar 7 6:49:00 2001
|
Hi everybody. From the list archives I see, that there was already a discussion going on last year, about an implementation of xr16 in VHDL. As VHDL is my preferrend implementation language, that I'm already using for an other project, I'm thinking of porting the xr16 Verilog code to VHDL, which should not a big deal, I think. Has anybody done this already? Greetings, Chris -- Christian Plessl < |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: VHDL Implementation of xr16 - Arrigo Benedetti - Mar 7 15:08:00 2001
|
Christian Plessl <> writes: > Hi everybody. > > From the list archives I see, that there was already a discussion going on > last year, about an implementation of xr16 in VHDL. As VHDL is my > preferrend implementation language, that I'm already using for an other > project, I'm thinking of porting the xr16 Verilog code to VHDL, which > should not a big deal, I think. > > Has anybody done this already? Yes, I have done it. Well, almost... I came to the point where I was checking the VHDL with the same test vectors used by Jan in his verilog simulation. There was still a glitch that I was tracing when I had to abandon this project for other work with higher priority. I think that what I have done is probably 95% of the work and I am more than happy to make it available. However, since my work is derived from Jan's work we need his consent before I can make it public. Actually we were discussing about this some time ago but I have not had any word from him since last summer. Best, -Arrigo -- Dr. Arrigo Benedetti o e-mail: Caltech, MS 136-93 < > phone: (626) 395-3129 Pasadena, CA 91125 / \ fax: (626) 795-8649 |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: VHDL Implementation of xr16 - Christian Plessl - Mar 8 3:05:00 2001
|
Hi Arrigo >Christian Plessl <> writes: > > From the list archives I see, that there was already a discussion > going on > > last year, about an implementation of xr16 in VHDL. As VHDL is my > > preferrend implementation language, that I'm already using for an other > > project, I'm thinking of porting the xr16 Verilog code to VHDL, which > > should not a big deal, I think. > > > > Has anybody done this already? > >Yes, I have done it. Well, almost... I came to the point where I was >checking the VHDL with the same test vectors used by Jan in his verilog >simulation. There was still a glitch that I was tracing when I had to >abandon this project for other work with higher priority. I think that >what I have done is probably 95% of the work and I am more than happy to >make it available. However, since my work is derived from Jan's work we >need his consent before I can make it public. Actually we were discussing >about this some time ago but I have not had any word from him since last >summer. That sounds interessting. It would be nice if you could recontribute the code, maybe Jan could include it in the ordinary distribution as well, don't know what he is thinking about it. Chris -- Christian Plessl < |
controlSUITE™ software. Comprehensive. Intuitive. Optimized.
Real-world software for real-time control. Details Here!
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )