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Discussion Groups | FPGA-CPU | Spartan2 or Virtex specific xr16/xr32
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Spartan2 or Virtex specific xr16/xr32 - Christian Plessl - Mar 7 6:55:00 2001
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Hi everybody. Jan Gray announced, that he we wants to "port" the XSOC system to Xilinx Spartan resp. Virtex architecture. As most of the architecture will be the same, the internal BlockRAM+ will allow a more elegant implementation of the register file. I cannot see any Virtex/Spartan related code anywhere on the fpgacpu homepage, am I missing something? One last question: What about the 32-bit version of xr16? Is there any ongoing work, or has this project been abandoned? Greetings, Chris -- Christian Plessl < |
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Re: Spartan2 or Virtex specific xr16/xr32 - Author Unknown - Mar 7 17:57:00 2001
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Hi, Chris, I have developed an xr16 implementation for Virtex/Spartan-II in Verilog, called xr16vx. I got very close to having it all tested and ready to go last month, when other things came up. It does pass xr16.s, but I have a snag on the real board, probably in my little PIO timer or its C code. I'll post a notice when it's ready, soon I hope. My xr16vx is not focused on minimum size, like Jan's. It's written for simplicity of synthesis and clarity of understanding. It uses BlockRAM for main memory, one port for instructions, the other for data. So it's very fast and self-contained. --Mike |
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Re: Re: Spartan2 or Virtex specific xr16/xr32 - Christian Plessl - Mar 8 3:10:00 2001
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Hi Mike >I have developed an xr16 implementation for Virtex/Spartan-II >in Verilog, called xr16vx. I got very close to having it all >tested and ready to go last month, when other things came up. >It does pass xr16.s, but I have a snag on the real board, probably >in my little PIO timer or its C code. That would be very nice of you. Although I'm planning to use VHDL for my experiments, your Verilog source might be a good starting point, I suppose. >My xr16vx is not focused on minimum size, like Jan's. It's written >for simplicity of synthesis and clarity of understanding. It uses >BlockRAM for main memory, one port for instructions, the other for >data. So it's very fast and self-contained. Sounds very interessting. Does it provide the possibility to attach memory through an external memory interface too? Your splitting in instruction and data memory, will facillitate the addition of data/instruction cache in future, I suppose. Hope to hear from you again soon. Cheers, Chris -- Christian Plessl < |
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