Sign in
Search fpga-cpu
Subscribe to fpga-cpu
fpga-cpu by Keywords
Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A
Ads
Discussion Groups
Discussion Groups | FPGA-CPU | v6502
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Re: v6502 - Ben Franchuk - Mar 8 21:59:00 2001
|
wrote: > > I started working on a verilog version of the 6502 processor > yesterday. I handcrafted a state machine based on observations of > opcode patterns and knowledge of the cpu. > I also downloaded webpack from Xilinx and tried ng the > design. After running synthesis for about 6 hours, I shut it down. > > My questions is, how long should it take to synthesize a design with > the webpack tools ? It's a fairly straight forward design, only about > 1500 lines of verilog. I just want to know roughly how big the design > is. Are there any options I can set to speed things up ? I use schematic entry as high level design costs $$$. Off hand I don't expect more than 5-15 minutes to synthesize the design. Routing and layout take the time in design.Using a different FPGA brand a normal design takes about 45 minutes, to layout and route. Ben. PS. I have read somewhere on the net that the 6502 is very nasty cpu to synthesize for a FPGA because some FPGA's handle random logic very poorly and the early CPU's had a large a amount that. Nobody wants to do a 6800 in a FPGA for some reason. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
v6502 - Author Unknown - Mar 9 12:00:00 2001
|
I started working on a verilog version of the 6502 processor yesterday. I handcrafted a state machine based on observations of opcode patterns and knowledge of the cpu. I also downloaded webpack from Xilinx and tried synthesizing the design. After running synthesis for about 6 hours, I shut it down. My questions is, how long should it take to synthesize a design with the webpack tools ? It's a fairly straight forward design, only about 1500 lines of verilog. I just want to know roughly how big the design is. Are there any options I can set to speed things up ? Thanks Rob |
|
|
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
RE: v6502 - Gary Watson - Mar 9 12:36:00 2001
|
Hi Rob, Are you aware of http://www.free-ip.com/6502/index.html ? I'm considering using it in designs since Jan won't let people use his stuff commercially. Best Regards, Gary Watson Chief Technology Officer Nexsan Technologies, Ltd. Imperial House East Service Road Raynesway Derby DE21 7BF ENGLAND +44 (0) 1332 5 444 33 http://www.nexsan.com > -----Original Message----- > From: [mailto:] > Sent: Friday, March 09, 2001 5:00 PM > To: > Subject: [fpga-cpu] v6502 > I started working on a verilog version of the 6502 processor > yesterday. I handcrafted a state machine based on observations of > opcode patterns and knowledge of the cpu. > I also downloaded webpack from Xilinx and tried synthesizing the > design. After running synthesis for about 6 hours, I shut it down. > > My questions is, how long should it take to synthesize a design with > the webpack tools ? It's a fairly straight forward design, only about > 1500 lines of verilog. I just want to know roughly how big the design > is. Are there any options I can set to speed things up ? > > Thanks > Rob > > To Post a message, send it to: > To Unsubscribe, send a blank message to: |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: v6502 - Author Unknown - Mar 9 16:20:00 2001
|
Well, I think this is an extremely long time. We are working in a project which has 200 KB of VHDL code, about 4000 lines of code. It synthesizes in about 2 minutes in a P3-450 (128 MB RAM) in low effort. If you try at highest effort then it takes less than 15 minutes. Perhaps your WEBPack crashed in the try... By the way, our design takes up 1000 slices. One thing I have noted is that if you use muxes as tristates, then the tool takes a lot more of time to synthesize: in low effort it doesn't take 2 but 10 minutes. I didn't try it on highest effort. Anyway, I think 6 hours are too much, unless you were using a Pentium-100 XD Bye. To: From: Date sent: Fri, 09 Mar 2001 17:00:00 -0000 Send reply to: Subject: [fpga-cpu] v6502 > I started working on a verilog version of the 6502 processor > yesterday. I handcrafted a state machine based on observations of > opcode patterns and knowledge of the cpu. > I also downloaded webpack from Xilinx and tried synthesizing the > design. After running synthesis for about 6 hours, I shut it down. > > My questions is, how long should it take to synthesize a design with > the webpack tools ? It's a fairly straight forward design, only about > 1500 lines of verilog. I just want to know roughly how big the design > is. Are there any options I can set to speed things up ? > > Thanks > Rob > > To Post a message, send it to: > To Unsubscribe, send a blank message to: > > ## ## # ## # # # # # # # # # # # # # # # # # # # # # # ## # # # # # # ## # # ## ##### # # # # # # # # # # # # # # # ## # # # # # # # # # # # # # # # # # # ## # # ### # # # # # # # # # # # # ## # # # # # # # # # # # ## # ## # # # # # # # # # ## # # # # ## # # # # # # # # #### # # # # # # # # # # # # # # # # # # # # # # # # # # # # ## ## ### ## ## ## ## #### |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: v6502 - Author Unknown - Mar 12 22:13:00 2001
|
I was able to get a version of the mpu to synthesize by using a state register instead of a bunch of state bits to implement the state machine. (Although it still did hang once during the optimization stage.) It looks like the synthesizer was having trouble extracting registers because it became very slow and eventually hung. My version of the 6502 on first synth came out to about 1000Luts and 33% of a S200. projected clock freq. 60MHz. I'm thinking of using this as a "virtual mode" processor for another another processor I'm working on like the "virtual 8086" mode of the 386.... |
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )