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rtstofer wrote:
> The Verilog might look like:
>
> assign result = (sig1 ? a : 1'b0) |
> (sig2 ? b : 1'b0) |
> (sig3 ? c : 1'b0);
>
> This results in 3 2-input AND gates and a 3 input OR gate. Oddly
> enough, it is slower at 10.648 nS and the Systhesis Report still lists
> 4 levels of logic. 7.567 nS attributed to logic versus 7.376 for the
> VHDL example. But, as more conditions are added, the delay won't
> increase. The OR gate will get wider and, I suppose there will be
> issues when it gets too wide but that's a lot better than the 23
> levels of logic I have for my naive VHDL interpretation of the ALU.
>
> Is there a way to code this Verilog construct in VHDL that doesn't
> result in a priority encoder? I would much prefer a MUX but I don't
> have a vector to use to select inputs.

If you want and & or gates, why not just say so, ie:

result <= ( a and sig1 ) or ( b and sig2) or ( c and sig3);

If you want to make something that more exactly matches the verilog
code, you could write a function to do the multiplexing or generate the
three intermediate signals and or them. The logic difference is coming
from your cascaded when...else statements, which is creating a
dependency between sig1/sig2/sig3 that doesn't exist in the verilog version.

Intermediate products:
amx <= a when sig1='1' else '0';
bmx <= b when sig2='1' else '0';
cmx <= c when sig3='1' else '0';
result <= amx or bmx or cmx;

Pretty-fied function version:
function my_mux (sig, x : in std_logic) return std_logic is
begin
if sig='1' then
return x;
else
return '0';
end if;
end;

...

result <= my_mux(sig1,a) or my_mux(sig2,b) or my_mux(sig3,c);

All three should compile into the same physical gates...

- --
Charles Steinkuehler
c...@newtek.com
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> If you want and & or gates, why not just say so, ie:
>
> result <= ( a and sig1 ) or ( b and sig2) or ( c and sig3);

In many cases 'a' is actually a vector...

>
> If you want to make something that more exactly matches the verilog
> code, you could write a function to do the multiplexing or generate the
> three intermediate signals and or them. The logic difference is coming
> from your cascaded when...else statements, which is creating a
> dependency between sig1/sig2/sig3 that doesn't exist in the verilog
version.
>
> Intermediate products:
> amx <= a when sig1='1' else '0';
> bmx <= b when sig2='1' else '0';
> cmx <= c when sig3='1' else '0';
> result <= amx or bmx or cmx;

This will work nicely even with vectors. I wonder if it is worth
messing around with tri-state to eliminate the 'or'?

>
> Pretty-fied function version:
> function my_mux (sig, x : in std_logic) return std_logic is
> begin
> if sig='1' then
> return x;
> else
> return '0';
> end if;
> end;
>
> ...
>
> result <= my_mux(sig1,a) or my_mux(sig2,b) or my_mux(sig3,c);
>
> All three should compile into the same physical gates...
>

Neat...

Thanks!
Richard

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> I wonder if it is worth
> messing around with tri-state to eliminate the 'or'?

No. By using tri-state, you're just forcing the synthesizer to
decide what to do, since the FPGA doesn't actually have tristate
busses internally. You're better off telling it explicitly what
you want.

Eric

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