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Consider something like:

result <= a when sig1 = '1' else
b when sig2 = '1' else
c when sig3 = '1' else
'0';

The XST synthesis tool infers a priority encoder. That's probably ok
when there are only 3 or 4 choices but it gets completely out of hand
when there are 16 choices. The number of logic levels becomes excessive.

The result here is 4 levels of logic, 2 2-input OR gates, 3 2-input
AND gates (one with an inverter on 1 input) and a 3-input AND gate
(with an inverter on 1 input) and the maximum delay is 9.393 nS, 7.376
nS for logic.

Now, XST doesn't know that sig1, sig2 and sig3 are mutually exclusive.
They are decoded op codes like 'add', 'sub', etc and decoded
elsewhere. This from the POP11 project where I have taken the
generated Verilog and tried to change it to VHDL.

The Verilog might look like:

assign result = (sig1 ? a : 1'b0) |
(sig2 ? b : 1'b0) |
(sig3 ? c : 1'b0);

This results in 3 2-input AND gates and a 3 input OR gate. Oddly
enough, it is slower at 10.648 nS and the Systhesis Report still lists
4 levels of logic. 7.567 nS attributed to logic versus 7.376 for the
VHDL example. But, as more conditions are added, the delay won't
increase. The OR gate will get wider and, I suppose there will be
issues when it gets too wide but that's a lot better than the 23
levels of logic I have for my naive VHDL interpretation of the ALU.

Is there a way to code this Verilog construct in VHDL that doesn't
result in a priority encoder? I would much prefer a MUX but I don't
have a vector to use to select inputs.

Or should I use this as a learning opportunity and use Verilog?

Thanks!
Richard

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You could do worse than check out
http://www.cs.tut.fi/soc/Metzgen04.pdf
Even though it's an Altera perspective, the general
principles holds true for Xilinx as well.

> Is there a way to code this Verilog construct in
> VHDL that doesn't
> result in a priority encoder? I would much prefer a
> MUX but I don't
> have a vector to use to select inputs.

If you can (especially if you know the selects ahead
of the data and can use a pipeline stage for that),
you're likely better off translating your bit-line
selects into an index and using that to drive the mux,
especially if the mux is wide. Fx (in Verilog,
untested)

wire [7:0] select;
reg [2:0] index;
always @(*)
casex (select)
8'b1xxxxxxx: index = 0;
8'bx1xxxxxx: index = 1;
...
8'bxxxxxxx1: index = 7;
default: index = 'hX;
endcase

wire [31:0] sig0, sig1, ..., sig7;
reg [31:0] res;
always @(*)
casex (index)
0: res = sig0;
....
7: res = sig7;
default: res = 'hX;
endcase
> Or should I use this as a learning opportunity and
> use Verilog?

Never a bad idea IMO.

Tommy

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> You could do worse than check out
> http://www.cs.tut.fi/soc/Metzgen04.pdf
> Even though it's an Altera perspective, the general
> principles holds true for Xilinx as well.

This one is even more explicitly on the mux issue:
Multiplexer Restructuring for FPGA Implementation Cost
Reduction
(http://www.soccentral.com/goto.asp?EntryID=14999)

Tommy

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--- In f...@yahoogroups.com, "Eric Smith" wrote:
>
> > Is there a way to code this Verilog construct in VHDL that doesn't
> > result in a priority encoder? I would much prefer a MUX but I don't
> > have a vector to use to select inputs.
>
> Sure, just use "or" like you did in the Verilog ("|") instead of a
> the "when" constructs.
>
> Eric
>

I should have mentioned that in many cases, the code is dealing with
vectors rather than individual signals.

I recoded the ALU in cleaned-up Verilog and compared it to VHDL. In
the end, there is one level difference. It's either 28 levels
(Verilog) or 29 levels (VHDL) for the PDP-11/40 ALU and the delays
(ignoring IBUF and OBUF) are on the order of 40 nS for a Spartan IIE
speed grade 6.

Given that the prototype only runs at 20 MHz, I still have a little
margin.

Another approach might be to break up the ALU into separate units:
adder, shifter, bit operations, etc. Then MUX the results. I have
seen some RISC designs that use that approach.

Richard

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> I should have mentioned that in many cases, the code is dealing with
> vectors rather than individual signals.

And that would be a problem because... ?

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> Another approach might be to break up the ALU into
> separate units:
> adder, shifter, bit operations, etc. Then MUX the
> results. I have
> seen some RISC designs that use that approach.

Actually, that *is* the classic approach, but
sometimes you can do better by merging operations or
being very clever with the implementation. See fx. "A
High Performance 32-bit ALU for Programmable Logic" in
FPGA'04. In my experience, those tricks doesn't really
help on "modern" FPGAs though, so as long as you keep
the muxes under control you'll be fine.

Quartus II will give you a ton of information about
the muxes it found and how many resources they take.
ISE might have something similar.

Tommy

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--- In f...@yahoogroups.com, "Eric Smith" wrote:
>
> > I should have mentioned that in many cases, the code is dealing with
> > vectors rather than individual signals.
>
> And that would be a problem because... ?
>

I guess I don't know how to do a vector assignment based on a logic
operation like:

some_vector <= (some_other_vector AND a_std_signal ) OR
(another_vector AND some_other_std_signal);

in an attempt to get rid of the WHEN - ELSE construct.

It would certainly work when everything is a std_signal.

Richard

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> I guess I don't know how to do a vector assignment based on a logic
> operation like:
>
> some_vector <= (some_other_vector AND a_std_signal ) OR
> (another_vector AND some_other_std_signal);

The logical operators are defined on std_logic_vector. The problem is
that they aren't defined between a std_logic_vector and a std_logic.
The easiest way to do this "inline" is to use an aggregate to expand
the std_logic signal into a vector:

some_vector <=
(some_other_vector and (some_other_vector'range => a_std_signal)) or
(another_vector and (another_vector'range => some_other_std_signal));

That's cumbersome to type, so a better approach may be to write your
own function to overload "and":

function "and" (a: std_logic_vector;
b: std_logic) return std_logic_vector is
begin
return a and (a'range => b);
end;

You can define that in your architecture (before the "begin", with your
types, signals, etc.), or you can put it in a separate package and "use"
it from multiple source files. Either way, you can then write:

some_vector <= (some_other_vector and a_std_signal) or
(another_vector and some_other_std_signal);

Of course, you don't have to overload the "and" operator. You could
define a function with a normal name such as andvs, and use that:

some_vector <= andvs (some_other_vector, a_std_signal) or
andvs (another_vector, some_other_std_signal);

I prefer the overloading as I think the result is more readable, but
some people don't seem to like overloading.

Eric

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> Is there a way to code this Verilog construct in VHDL that doesn't
> result in a priority encoder? I would much prefer a MUX but I don't
> have a vector to use to select inputs.

Sure, just use "or" like you did in the Verilog ("|") instead of a
the "when" constructs.

Eric

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--- In f...@yahoogroups.com, "rtstofer" wrote:
>
> Consider something like:
>
> result <= a when sig1 = '1' else
> b when sig2 = '1' else
> c when sig3 = '1' else
> '0';
>
> The XST synthesis tool infers a priority encoder.
>
Is there a way to code this Verilog construct
> in VHDL that doesn't result in a priority encoder?
>

I usually use the with..select concurrent assignment
for something like that.


constant T_MOV : std_logic_vector( OP_MSB downto 0) := B"00";
constant T_AND : std_logic_vector( OP_MSB downto 0) := B"01";
constant T_OR : std_logic_vector( OP_MSB downto 0) := B"10";
constant T_XOR : std_logic_vector( OP_MSB downto 0) := B"11";



with logic_op select
logic_dat <=
ain AND logic_bin when T_AND,
ain OR logic_bin when T_OR,
ain XOR logic_bin when T_XOR,
logic_bin when T_MOV,

(others => 'X') when others;
If you need to paste together signals for a case/select
statement, define a subtype first like this:

subtype slv_4b is std_logic_vector(3 downto 0);
...
with slv_4b'( mem_size & mem_ea_dat(1 downto 0) ) select
Also of note, XST will support don't cares ('?') in
case/select choices, but I don't believe all synthesis
tools will accept this.

Brian

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--- In f...@yahoogroups.com, "Eric Smith" wrote:
>
> > I guess I don't know how to do a vector assignment based on a logic
> > operation like:
> >
> > some_vector <= (some_other_vector AND a_std_signal ) OR
> > (another_vector AND some_other_std_signal);
>
> The logical operators are defined on std_logic_vector. The problem is
> that they aren't defined between a std_logic_vector and a std_logic.
> The easiest way to do this "inline" is to use an aggregate to expand
> the std_logic signal into a vector:
>
> some_vector <=
> (some_other_vector and (some_other_vector'range =>
a_std_signal)) or
> (another_vector and (another_vector'range =>
some_other_std_signal));
>
> That's cumbersome to type, so a better approach may be to write your
> own function to overload "and":
>
> function "and" (a: std_logic_vector;
> b: std_logic) return std_logic_vector is
> begin
> return a and (a'range => b);
> end;
>
> You can define that in your architecture (before the "begin", with your
> types, signals, etc.), or you can put it in a separate package and "use"
> it from multiple source files. Either way, you can then write:
>
> some_vector <= (some_other_vector and a_std_signal) or
> (another_vector and some_other_std_signal);
>
> Of course, you don't have to overload the "and" operator. You could
> define a function with a normal name such as andvs, and use that:
>
> some_vector <= andvs (some_other_vector, a_std_signal) or
> andvs (another_vector, some_other_std_signal);
>
> I prefer the overloading as I think the result is more readable, but
> some people don't seem to like overloading.
>
> Eric
>
I knew I would learn a lot when I posted this question. Yours is an
interesting solution!

I'll synthesize it tomorrow and see what it looks like...

Thanks
Richard

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