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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
RISC Basic IS - ~*Bushra Qamar*~ - Jan 21 3:39:38 2008
Hi,
Im doing Bsc in electrical engineering....im in 7th semester....i'm
doing work on RISC processor as the mini project....when i tried the
control unit and data path seperatley on fpga it runs well...but when
i combined both...xilinx gives error"there is no processing in the
design....Design in empty...."i could not understand how to solve this
problem....can anay one plz help me..if u say i can paste my code
there also...
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Im doing Bsc in electrical engineering....im in 7th semester....i'm
doing work on RISC processor as the mini project....when i tried the
control unit and data path seperatley on fpga it runs well...but when
i combined both...xilinx gives error"there is no processing in the
design....Design in empty...."i could not understand how to solve this
problem....can anay one plz help me..if u say i can paste my code
there also...
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
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Re: RISC Basic IS - rtstofer - Jan 21 10:42:56 2008
--- In f...@yahoogroups.com, "~*Bushra Qamar*~"
wrote:
>
> Hi,
> Im doing Bsc in electrical engineering....im in 7th semester....i'm
> doing work on RISC processor as the mini project....when i tried the
> control unit and data path seperatley on fpga it runs well...but when
> i combined both...xilinx gives error"there is no processing in the
> design....Design in empty...."i could not understand how to solve this
> problem....can anay one plz help me..if u say i can paste my code
> there also...
>
Do you have external inputs and outputs defined? I think I have had
this error when I hadn't declared the I/O.
You can also search at Xilinx. Each message has a number and you can
usually find something that explains the error and what to do to
correct it.
Richard
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wrote:
>
> Hi,
> Im doing Bsc in electrical engineering....im in 7th semester....i'm
> doing work on RISC processor as the mini project....when i tried the
> control unit and data path seperatley on fpga it runs well...but when
> i combined both...xilinx gives error"there is no processing in the
> design....Design in empty...."i could not understand how to solve this
> problem....can anay one plz help me..if u say i can paste my code
> there also...
>
Do you have external inputs and outputs defined? I think I have had
this error when I hadn't declared the I/O.
You can also search at Xilinx. Each message has a number and you can
usually find something that explains the error and what to do to
correct it.
Richard
To post a message, send it to: f...@yahoogroups.com
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Re: Re: RISC Basic IS - muhammad yasin - Jan 22 22:22:47 2008
Hi I hope the problem willl have been solved
Apart from previous answer(defining I/O's) ... Mistake people make is not to
declare the interconnecting wires
As far as I/O's are concerned define just some random output and assign it
something from your processor ... All will be fine
Hope that helps
On 1/21/08, rtstofer wrote:
>
> --- In f...@yahoogroups.com, "~*Bushra
> Qamar*~"
> wrote:
> >
> > Hi,
> > Im doing Bsc in electrical engineering....im in 7th semester....i'm
> > doing work on RISC processor as the mini project....when i tried the
> > control unit and data path seperatley on fpga it runs well...but when
> > i combined both...xilinx gives error"there is no processing in the
> > design....Design in empty...."i could not understand how to solve this
> > problem....can anay one plz help me..if u say i can paste my code
> > there also...
> > Do you have external inputs and outputs defined? I think I have had
> this error when I hadn't declared the I/O.
>
> You can also search at Xilinx. Each message has a number and you can
> usually find something that explains the error and what to do to
> correct it.
>
> Richard
>
[Non-text portions of this message have been removed]
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Apart from previous answer(defining I/O's) ... Mistake people make is not to
declare the interconnecting wires
As far as I/O's are concerned define just some random output and assign it
something from your processor ... All will be fine
Hope that helps
On 1/21/08, rtstofer
>
> --- In f...@yahoogroups.com
> Qamar*~"
> wrote:
> >
> > Hi,
> > Im doing Bsc in electrical engineering....im in 7th semester....i'm
> > doing work on RISC processor as the mini project....when i tried the
> > control unit and data path seperatley on fpga it runs well...but when
> > i combined both...xilinx gives error"there is no processing in the
> > design....Design in empty...."i could not understand how to solve this
> > problem....can anay one plz help me..if u say i can paste my code
> > there also...
> > Do you have external inputs and outputs defined? I think I have had
> this error when I hadn't declared the I/O.
>
> You can also search at Xilinx. Each message has a number and you can
> usually find something that explains the error and what to do to
> correct it.
>
> Richard
>
[Non-text portions of this message have been removed]
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Re: Re: RISC Basic IS - Kolja Sulimma - Jan 25 7:07:33 2008
Synthesis tools usually trim any logic that produces results that are not
used anywhere.
They guarantee to produce the output that you specified. If you did not
specify any output
the job is easy for the tool: Delete everything.
Kolja Sulimma
2008/1/24, Bushra Qamar:
>
> Yes,I have declared CLK,REST as inputs.and all the
> data is processed on clok edge
> but i dont display it any where..is that my fault???
> infact i dont need to display that...but should i?
> --- muhammad yasin>
> wrote:
>
> > Hi I hope the problem willl have been solved
> >
> > Apart from previous answer(defining I/O's) ...
> > Mistake people make is not to
> > declare the interconnecting wires
> >
> > As far as I/O's are concerned define just some
> > random output and assign it
> > something from your processor ... All will be fine
> > Hope that helps
> >
> >
> > On 1/21/08, rtstofer>
> wrote:
> > >
> > > --- In f...@yahoogroups.com
> >, "~*Bushra
> > > Qamar*~"
> > > wrote:
> > > >
> > > > Hi,
> > > > Im doing Bsc in electrical engineering....im in
> > 7th semester....i'm
> > > > doing work on RISC processor as the mini
> > project....when i tried the
> > > > control unit and data path seperatley on fpga it
> > runs well...but when
> > > > i combined both...xilinx gives error"there is no
> > processing in the
> > > > design....Design in empty...."i could not
> > understand how to solve this
> > > > problem....can anay one plz help me..if u say i
> > can paste my code
> > > > there also...
> > > >
> > >
> > > Do you have external inputs and outputs defined? I
> > think I have had
> > > this error when I hadn't declared the I/O.
> > >
> > > You can also search at Xilinx. Each message has a
> > number and you can
> > > usually find something that explains the error and
> > what to do to
> > > correct it.
> > >
> > > Richard
> > >
> > >
> > >
> >
> >
> > [Non-text portions of this message have been
> > removed]
> >
> > __________________________________________________________
> Looking for last minute shopping deals?
> Find them fast with Yahoo! Search.
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
>
>
--
cronologic ohg Frankfurt am Main
HRA 42869 beim Amtsgericht Frankfurt
Telefon 069 38 09 78 254
[Non-text portions of this message have been removed]
To post a message, send it to: f...@yahoogroups.com
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______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
used anywhere.
They guarantee to produce the output that you specified. If you did not
specify any output
the job is easy for the tool: Delete everything.
Kolja Sulimma
2008/1/24, Bushra Qamar
>
> Yes,I have declared CLK,REST as inputs.and all the
> data is processed on clok edge
> but i dont display it any where..is that my fault???
> infact i dont need to display that...but should i?
> --- muhammad yasin
> wrote:
>
> > Hi I hope the problem willl have been solved
> >
> > Apart from previous answer(defining I/O's) ...
> > Mistake people make is not to
> > declare the interconnecting wires
> >
> > As far as I/O's are concerned define just some
> > random output and assign it
> > something from your processor ... All will be fine
> > Hope that helps
> >
> >
> > On 1/21/08, rtstofer
> wrote:
> > >
> > > --- In f...@yahoogroups.com
> >
> > > Qamar*~"
> > > wrote:
> > > >
> > > > Hi,
> > > > Im doing Bsc in electrical engineering....im in
> > 7th semester....i'm
> > > > doing work on RISC processor as the mini
> > project....when i tried the
> > > > control unit and data path seperatley on fpga it
> > runs well...but when
> > > > i combined both...xilinx gives error"there is no
> > processing in the
> > > > design....Design in empty...."i could not
> > understand how to solve this
> > > > problem....can anay one plz help me..if u say i
> > can paste my code
> > > > there also...
> > > >
> > >
> > > Do you have external inputs and outputs defined? I
> > think I have had
> > > this error when I hadn't declared the I/O.
> > >
> > > You can also search at Xilinx. Each message has a
> > number and you can
> > > usually find something that explains the error and
> > what to do to
> > > correct it.
> > >
> > > Richard
> > >
> > >
> > >
> >
> >
> > [Non-text portions of this message have been
> > removed]
> >
> > __________________________________________________________
> Looking for last minute shopping deals?
> Find them fast with Yahoo! Search.
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
>
>
--
cronologic ohg Frankfurt am Main
HRA 42869 beim Amtsgericht Frankfurt
Telefon 069 38 09 78 254
[Non-text portions of this message have been removed]
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: RISC Basic IS - muhammad yasin - Jan 26 3:11:03 2008
Oh yes ,.... problem is that
if an output of your module is not to be used anywhere
synthesizer takes it as uselsess and discards
thats why u should just for fun add something as output ... e.g. the output
of ALU
On 1/25/08, Bushra Qamar wrote:
>
> Yes,I have declared CLK,REST as inputs.and all the
> data is processed on clok edge
> but i dont display it any where..is that my fault???
> infact i dont need to display that...but should i?
> --- muhammad yasin>
> wrote:
>
> > Hi I hope the problem willl have been solved
> >
> > Apart from previous answer(defining I/O's) ...
> > Mistake people make is not to
> > declare the interconnecting wires
> >
> > As far as I/O's are concerned define just some
> > random output and assign it
> > something from your processor ... All will be fine
> > Hope that helps
> >
> >
> > On 1/21/08, rtstofer>
> wrote:
> > >
> > > --- In f...@yahoogroups.com
> >, "~*Bushra
> > > Qamar*~"
> > > wrote:
> > > >
> > > > Hi,
> > > > Im doing Bsc in electrical engineering....im in
> > 7th semester....i'm
> > > > doing work on RISC processor as the mini
> > project....when i tried the
> > > > control unit and data path seperatley on fpga it
> > runs well...but when
> > > > i combined both...xilinx gives error"there is no
> > processing in the
> > > > design....Design in empty...."i could not
> > understand how to solve this
> > > > problem....can anay one plz help me..if u say i
> > can paste my code
> > > > there also...
> > > >
> > >
> > > Do you have external inputs and outputs defined? I
> > think I have had
> > > this error when I hadn't declared the I/O.
> > >
> > > You can also search at Xilinx. Each message has a
> > number and you can
> > > usually find something that explains the error and
> > what to do to
> > > correct it.
> > >
> > > Richard
> > >
> > >
> > >
> >
> >
> > [Non-text portions of this message have been
> > removed]
> >
> > __________________________________________________________
> Looking for last minute shopping deals?
> Find them fast with Yahoo! Search.
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
>
[Non-text portions of this message have been removed]
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
if an output of your module is not to be used anywhere
synthesizer takes it as uselsess and discards
thats why u should just for fun add something as output ... e.g. the output
of ALU
On 1/25/08, Bushra Qamar
>
> Yes,I have declared CLK,REST as inputs.and all the
> data is processed on clok edge
> but i dont display it any where..is that my fault???
> infact i dont need to display that...but should i?
> --- muhammad yasin
> wrote:
>
> > Hi I hope the problem willl have been solved
> >
> > Apart from previous answer(defining I/O's) ...
> > Mistake people make is not to
> > declare the interconnecting wires
> >
> > As far as I/O's are concerned define just some
> > random output and assign it
> > something from your processor ... All will be fine
> > Hope that helps
> >
> >
> > On 1/21/08, rtstofer
> wrote:
> > >
> > > --- In f...@yahoogroups.com
> >
> > > Qamar*~"
> > > wrote:
> > > >
> > > > Hi,
> > > > Im doing Bsc in electrical engineering....im in
> > 7th semester....i'm
> > > > doing work on RISC processor as the mini
> > project....when i tried the
> > > > control unit and data path seperatley on fpga it
> > runs well...but when
> > > > i combined both...xilinx gives error"there is no
> > processing in the
> > > > design....Design in empty...."i could not
> > understand how to solve this
> > > > problem....can anay one plz help me..if u say i
> > can paste my code
> > > > there also...
> > > >
> > >
> > > Do you have external inputs and outputs defined? I
> > think I have had
> > > this error when I hadn't declared the I/O.
> > >
> > > You can also search at Xilinx. Each message has a
> > number and you can
> > > usually find something that explains the error and
> > what to do to
> > > correct it.
> > >
> > > Richard
> > >
> > >
> > >
> >
> >
> > [Non-text portions of this message have been
> > removed]
> >
> > __________________________________________________________
> Looking for last minute shopping deals?
> Find them fast with Yahoo! Search.
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
>
[Non-text portions of this message have been removed]
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Re: RISC Basic IS - Bushra Qamar - Jan 26 11:24:06 2008
Yes,I have declared CLK,REST as inputs.and all the
data is processed on clok edge
but i dont display it any where..is that my fault???
infact i dont need to display that...but should i?
--- muhammad yasin wrote:
> Hi I hope the problem willl have been solved
>
> Apart from previous answer(defining I/O's) ...
> Mistake people make is not to
> declare the interconnecting wires
>
> As far as I/O's are concerned define just some
> random output and assign it
> something from your processor ... All will be fine
> Hope that helps
> On 1/21/08, rtstofer wrote:
> >
> > --- In f...@yahoogroups.com
>, "~*Bushra
> > Qamar*~"
> > wrote:
> > >
> > > Hi,
> > > Im doing Bsc in electrical engineering....im in
> 7th semester....i'm
> > > doing work on RISC processor as the mini
> project....when i tried the
> > > control unit and data path seperatley on fpga it
> runs well...but when
> > > i combined both...xilinx gives error"there is no
> processing in the
> > > design....Design in empty...."i could not
> understand how to solve this
> > > problem....can anay one plz help me..if u say i
> can paste my code
> > > there also...
> > >
> >
> > Do you have external inputs and outputs defined? I
> think I have had
> > this error when I hadn't declared the I/O.
> >
> > You can also search at Xilinx. Each message has a
> number and you can
> > usually find something that explains the error and
> what to do to
> > correct it.
> >
> > Richard
> >
> >
> >
> [Non-text portions of this message have been
> removed]
____________________________________________________________________________________
Looking for last minute shopping deals?
Find them fast with Yahoo! Search. http://tools.search.yahoo.com/newsearch/category.php?category=shopping
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data is processed on clok edge
but i dont display it any where..is that my fault???
infact i dont need to display that...but should i?
--- muhammad yasin
> Hi I hope the problem willl have been solved
>
> Apart from previous answer(defining I/O's) ...
> Mistake people make is not to
> declare the interconnecting wires
>
> As far as I/O's are concerned define just some
> random output and assign it
> something from your processor ... All will be fine
> Hope that helps
> On 1/21/08, rtstofer
> >
> > --- In f...@yahoogroups.com
>
> > Qamar*~"
> > wrote:
> > >
> > > Hi,
> > > Im doing Bsc in electrical engineering....im in
> 7th semester....i'm
> > > doing work on RISC processor as the mini
> project....when i tried the
> > > control unit and data path seperatley on fpga it
> runs well...but when
> > > i combined both...xilinx gives error"there is no
> processing in the
> > > design....Design in empty...."i could not
> understand how to solve this
> > > problem....can anay one plz help me..if u say i
> can paste my code
> > > there also...
> > >
> >
> > Do you have external inputs and outputs defined? I
> think I have had
> > this error when I hadn't declared the I/O.
> >
> > You can also search at Xilinx. Each message has a
> number and you can
> > usually find something that explains the error and
> what to do to
> > correct it.
> >
> > Richard
> >
> >
> >
> [Non-text portions of this message have been
> removed]
____________________________________________________________________________________
Looking for last minute shopping deals?
Find them fast with Yahoo! Search. http://tools.search.yahoo.com/newsearch/category.php?category=shopping
To post a message, send it to: f...@yahoogroups.com
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Re: RISC Basic IS - rtstofer - Jan 26 21:45:42 2008
--- In f...@yahoogroups.com, Bushra Qamar wrote:
>
> Yes,I have declared CLK,REST as inputs.and all the
> data is processed on clok edge
> but i dont display it any where..is that my fault???
> infact i dont need to display that...but should i?
> --- muhammad yasin wrote:
>
If the design doesn't have any outputs, the tools assume you are
building a space heater and, in an attempt to save energy, collapse
all the logic.
Any logic that isn't contributing to an output will also be omitted.
Say you define a flop but the output is never used: the tools will
just delete it from the design.
Richard
Richard
> > Hi I hope the problem willl have been solved
> >
> > Apart from previous answer(defining I/O's) ...
> > Mistake people make is not to
> > declare the interconnecting wires
> >
> > As far as I/O's are concerned define just some
> > random output and assign it
> > something from your processor ... All will be fine
> > Hope that helps
> >
> >
> > On 1/21/08, rtstofer wrote:
> > >
> > > --- In f...@yahoogroups.com
> >, "~*Bushra
> > > Qamar*~"
> > > wrote:
> > > >
> > > > Hi,
> > > > Im doing Bsc in electrical engineering....im in
> > 7th semester....i'm
> > > > doing work on RISC processor as the mini
> > project....when i tried the
> > > > control unit and data path seperatley on fpga it
> > runs well...but when
> > > > i combined both...xilinx gives error"there is no
> > processing in the
> > > > design....Design in empty...."i could not
> > understand how to solve this
> > > > problem....can anay one plz help me..if u say i
> > can paste my code
> > > > there also...
> > > >
> > >
> > > Do you have external inputs and outputs defined? I
> > think I have had
> > > this error when I hadn't declared the I/O.
> > >
> > > You can also search at Xilinx. Each message has a
> > number and you can
> > > usually find something that explains the error and
> > what to do to
> > > correct it.
> > >
> > > Richard
> > >
> > >
> > >
> >
> >
> > [Non-text portions of this message have been
> > removed]
> >
> >
____________________________________________________________________________________
> Looking for last minute shopping deals?
> Find them fast with Yahoo! Search.
http://tools.search.yahoo.com/newsearch/category.php?category=shopping
>
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>
> Yes,I have declared CLK,REST as inputs.and all the
> data is processed on clok edge
> but i dont display it any where..is that my fault???
> infact i dont need to display that...but should i?
> --- muhammad yasin
>
If the design doesn't have any outputs, the tools assume you are
building a space heater and, in an attempt to save energy, collapse
all the logic.
Any logic that isn't contributing to an output will also be omitted.
Say you define a flop but the output is never used: the tools will
just delete it from the design.
Richard
Richard
> > Hi I hope the problem willl have been solved
> >
> > Apart from previous answer(defining I/O's) ...
> > Mistake people make is not to
> > declare the interconnecting wires
> >
> > As far as I/O's are concerned define just some
> > random output and assign it
> > something from your processor ... All will be fine
> > Hope that helps
> >
> >
> > On 1/21/08, rtstofer
> > >
> > > --- In f...@yahoogroups.com
> >
> > > Qamar*~"
> > > wrote:
> > > >
> > > > Hi,
> > > > Im doing Bsc in electrical engineering....im in
> > 7th semester....i'm
> > > > doing work on RISC processor as the mini
> > project....when i tried the
> > > > control unit and data path seperatley on fpga it
> > runs well...but when
> > > > i combined both...xilinx gives error"there is no
> > processing in the
> > > > design....Design in empty...."i could not
> > understand how to solve this
> > > > problem....can anay one plz help me..if u say i
> > can paste my code
> > > > there also...
> > > >
> > >
> > > Do you have external inputs and outputs defined? I
> > think I have had
> > > this error when I hadn't declared the I/O.
> > >
> > > You can also search at Xilinx. Each message has a
> > number and you can
> > > usually find something that explains the error and
> > what to do to
> > > correct it.
> > >
> > > Richard
> > >
> > >
> > >
> >
> >
> > [Non-text portions of this message have been
> > removed]
> >
> >
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Re: Re: RISC Basic IS - Bushra Qamar - Jan 27 9:15:27 2008
okies:)
thanx for the help,i dipslayed the contents of
registers...it works now very welll:)
--- muhammad yasin wrote:
> Oh yes ,.... problem is that
>
> if an output of your module is not to be used
> anywhere
>
> synthesizer takes it as uselsess and discards
>
> thats why u should just for fun add something as
> output ... e.g. the output
> of ALU
> On 1/25/08, Bushra Qamar
> wrote:
> >
> > Yes,I have declared CLK,REST as inputs.and all
> the
> > data is processed on clok edge
> > but i dont display it any where..is that my
> fault???
> > infact i dont need to display that...but should i?
> > --- muhammad yasin>
> > wrote:
> >
> > > Hi I hope the problem willl have been solved
> > >
> > > Apart from previous answer(defining I/O's) ...
> > > Mistake people make is not to
> > > declare the interconnecting wires
> > >
> > > As far as I/O's are concerned define just some
> > > random output and assign it
> > > something from your processor ... All will be
> fine
> > > Hope that helps
> > >
> > >
> > > On 1/21/08, rtstofer>
> > wrote:
> > > >
> > > > --- In f...@yahoogroups.com
>
> > >, "~*Bushra
> > > > Qamar*~"
> > > > wrote:
> > > > >
> > > > > Hi,
> > > > > Im doing Bsc in electrical engineering....im
> in
> > > 7th semester....i'm
> > > > > doing work on RISC processor as the mini
> > > project....when i tried the
> > > > > control unit and data path seperatley on
> fpga it
> > > runs well...but when
> > > > > i combined both...xilinx gives error"there
> is no
> > > processing in the
> > > > > design....Design in empty...."i could not
> > > understand how to solve this
> > > > > problem....can anay one plz help me..if u
> say i
> > > can paste my code
> > > > > there also...
> > > > >
> > > >
> > > > Do you have external inputs and outputs
> defined? I
> > > think I have had
> > > > this error when I hadn't declared the I/O.
> > > >
> > > > You can also search at Xilinx. Each message
> has a
> > > number and you can
> > > > usually find something that explains the error
> and
> > > what to do to
> > > > correct it.
> > > >
> > > > Richard
> > > >
> > > >
> > > >
> > >
> > >
> > > [Non-text portions of this message have been
> > > removed]
> > >
> > >
> >
> __________________________________________________________
> > Looking for last minute shopping deals?
> > Find them fast with Yahoo! Search.
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
> >
> >
> >
> [Non-text portions of this message have been
> removed]
____________________________________________________________________________________
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thanx for the help,i dipslayed the contents of
registers...it works now very welll:)
--- muhammad yasin
> Oh yes ,.... problem is that
>
> if an output of your module is not to be used
> anywhere
>
> synthesizer takes it as uselsess and discards
>
> thats why u should just for fun add something as
> output ... e.g. the output
> of ALU
> On 1/25/08, Bushra Qamar
> wrote:
> >
> > Yes,I have declared CLK,REST as inputs.and all
> the
> > data is processed on clok edge
> > but i dont display it any where..is that my
> fault???
> > infact i dont need to display that...but should i?
> > --- muhammad yasin
> > wrote:
> >
> > > Hi I hope the problem willl have been solved
> > >
> > > Apart from previous answer(defining I/O's) ...
> > > Mistake people make is not to
> > > declare the interconnecting wires
> > >
> > > As far as I/O's are concerned define just some
> > > random output and assign it
> > > something from your processor ... All will be
> fine
> > > Hope that helps
> > >
> > >
> > > On 1/21/08, rtstofer
> > wrote:
> > > >
> > > > --- In f...@yahoogroups.com
>
> > >
> > > > Qamar*~"
> > > > wrote:
> > > > >
> > > > > Hi,
> > > > > Im doing Bsc in electrical engineering....im
> in
> > > 7th semester....i'm
> > > > > doing work on RISC processor as the mini
> > > project....when i tried the
> > > > > control unit and data path seperatley on
> fpga it
> > > runs well...but when
> > > > > i combined both...xilinx gives error"there
> is no
> > > processing in the
> > > > > design....Design in empty...."i could not
> > > understand how to solve this
> > > > > problem....can anay one plz help me..if u
> say i
> > > can paste my code
> > > > > there also...
> > > > >
> > > >
> > > > Do you have external inputs and outputs
> defined? I
> > > think I have had
> > > > this error when I hadn't declared the I/O.
> > > >
> > > > You can also search at Xilinx. Each message
> has a
> > > number and you can
> > > > usually find something that explains the error
> and
> > > what to do to
> > > > correct it.
> > > >
> > > > Richard
> > > >
> > > >
> > > >
> > >
> > >
> > > [Non-text portions of this message have been
> > > removed]
> > >
> > >
> >
> __________________________________________________________
> > Looking for last minute shopping deals?
> > Find them fast with Yahoo! Search.
> http://tools.search.yahoo.com/newsearch/category.php?category=shopping
> >
> >
> >
> [Non-text portions of this message have been
> removed]
____________________________________________________________________________________
Looking for last minute shopping deals?
Find them fast with Yahoo! Search. http://tools.search.yahoo.com/newsearch/category.php?category=shopping
To post a message, send it to: f...@yahoogroups.com
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______________________________
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(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )