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Hi all,

I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3
development board from Altera.

I'm opening the example of Nios II system made by Altera.
But i get the following error when I try to generate it.
What error is this?

On the other hand, what is the best way to save a stream of data into
SDRAM? or would it be better if I made a soft memory for this purpose?
Regards,
Sim

Altera SOPC Builder Version 6.10 Build 201
Copyright (c) 1999-2006 Altera Corporation. All rights reserved.

# 2008.03.05 22:02:10 (*) mk_custom_sdk starting
# 2008.03.05 22:02:10 (*) Reading project C:/Documents and
Settings/yaNGz/Desktop/NiosII_On_UP3/SystemTop.ptf.
# 2008.03.05 22:02:10 (*) Finding all CPUs
# 2008.03.05 22:02:10 (*) Finding all available components
# 2008.03.05 22:02:10 (*) Reading C:/Documents and
Settings/yaNGz/Desktop/NiosII_On_UP3/.sopc_builder/install.ptf
# 2008.03.05 22:02:11 (*) Found 75 components
# 2008.03.05 22:02:12 (*) Finding all peripherals
# 2008.03.05 22:02:12 (*) Finding software components
# 2008.03.05 22:02:13 (*) (Legacy SDK Generation Skipped)
# 2008.03.05 22:02:13 (*) (All TCL Script Generation Skipped)
# 2008.03.05 22:02:13 (*) (No Libraries Built)
# 2008.03.05 22:02:13 (*) (Contents Generation Skipped)
# 2008.03.05 22:02:13 (*) mk_custom_sdk finishing
# 2008.03.05 22:02:13 (*) Starting generation for system: SystemTop.
.....
# 2008.03.05 22:02:15 (*) Running Generator Program for cpu_0
# 2008.03.05 22:02:17 (*) Checking for plaintext license.
# 2008.03.05 22:02:18 (*) Plaintext license not found.
# 2008.03.05 22:02:18 (*) Checking for encrypted license
(non-evaluation).
# 2008.03.05 22:02:18 (*) Encrypted license not found. Defaulting
to OCP evaluation license (produces a time-limited SOF)

ERROR:
In object '' of class e_process: can't access `user_attributes_names'
field
known fields are:
_AUTOLOAD_ACCEPT_ALL
_asynchronous_contents
_built
_clock
_contents
_creation_history
_object_list
_order
_parent_set
_project_set
_reset
_reset_default
_signal_list
_vhdl_files
_vhdl_fixes
_vhdl_variables
clock_level
comment
indent
isa_dummy
name
output_as_muxes_and_registers
paragraph
reset_level
sensitivity_list
known pointers are:
_parent
_project
keys:
_AUTOLOAD_ACCEPT_ALL
_permitted
_pointers
by the way, this object is a dummy

Error: Generator program
for module 'cpu_0' did NOT run successfully.
generator cmd was 'c:/altera/61/quartus//bin/perl/bin/perl
-Ic:/altera/61/quartus/sopc_builder/bin
-Ic:/altera/61/quartus/sopc_builder/bin/europa
-Ic:/altera/61/quartus/sopc_builder/bin/perl_lib -I.
-IC:/altera/72sp2/ip/nios2_ip/altera_nios2
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_onchip_memory2
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_onchip_memory
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_mutex
-IC:/Documents and
Settings/yaNGz/Desktop/NiosII_On_UP3/sls_sram_16_bit
-Ic:/altera/kits/nios/components/altera_plugs_library
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_cf
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_user_defined_interface
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_stratix_2s60_rohs
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_custom_instr_bitswap
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_cfi_flash
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_pll
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_sgdma
-Ic:/altera/61/quartus/sopc_builder/components/sls_tristate_16x2_character_lcd
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_epcs_flash_controller
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_adapter_upstream_pipeline
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_kit_stratix_edition_sram
-IC:/altera/72sp2/ip/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_lan91c111
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_kit_stratix_edition_sram2
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_adapter_downstream_pipeline
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_uart
-IC:/altera/72sp2/ip/ddr2_high_perf/lib/sopc_builder/ddr2_high_perf
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_adapter_waitrequest_pipeline
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_adapter_slave_y
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_asmi
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_custom_instr_endian_converter
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_jtag_uart
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_adapter_master_y
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_cyclone_1c20
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_tri_state_bridge
-IC:/altera/72sp2/ip/sopc_builder_ip/no_legacy_module
-IC:/altera/72sp2/ip/sopc_builder_ip/amd_avalon_am29lv128m_flash
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_cy7c1380_ssram
-Ic:/altera/kits/nios/components/altera_nios
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_cs8900
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_timer
-IC:/altera/72sp2/ip/ddr3_high_perf/lib/sopc_builder/ddr3_high_perf
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_dma
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_stratix_1s10
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_pio
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_custom_instruction
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_custom_instr_interrupt_vector
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_burst_adapter
-IC:/altera/72sp2/ip/pci_express_compiler/lib/sopc_builder/altera_avalon_pcie_compiler_adapter
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_spi
-IC:/altera/72sp2/ip/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_pipeline_bridge
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_sopc_builder
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_custom_instr_floating_point
-IC:/altera/72sp2/ip/triple_speed_ethernet/lib/sopc_builder/altera_triple_speed_ethernet
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_stratix_1s40
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_new_sdram_controller
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_clock_adapter
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_mailbox
-Ic:/altera/kits/nios/components/altera_nios_dev_board_sram32
-IC:/altera/72sp2/ip/pci_compiler/lib/sopc_builder/altera_avalon_pci_compiler_adapter
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_lcd_16207
-IC:/altera/72sp2/ip/sopc_builder_ip/amd_avalon_am29lv065d_flash
-Ic:/altera/kits/nios/components/altera_nios_dev_board_flash
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_endian_adapter
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_stratix_1s10_es
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_cyclone_2c35
-IC:/altera/72sp2/ip/nios2_ip/altera_nios2
-IC:/altera/72sp2/ip/ddr_ddr2_sdram/lib/sopc_builder/ddr_sdram_component
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_performance_counter
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_sysid
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_fifo
-IC:/altera/72sp2/ip/ddr_high_perf/lib/sopc_builder/ddr_high_perf
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_stratix_2s60_es
-IC:/altera/72sp2/ip/ddr_ddr2_sdram/lib/sopc_builder/ddr2_sdram_component
-Ic:/altera/kits/nios/components/altera_nios_custom_instr_divide
-Ic:/altera/kits/nios/components/altera_avalon_sdram_controller
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_multiply
-IC:/altera/72sp2/ip/sopc_builder_ip/altera_avalon_clock_crossing
-IC:/altera/72sp2/ip/nios2_ip/altera_nios_dev_board_stratix_2s60
C:/altera/72sp2/ip/nios2_ip/altera_nios2/cpu_core_select.pl
--system_name=SystemTop --target_module_name=cpu_0
--system_directory=C:/Documents and
Settings/yaNGz/Desktop/NiosII_On_UP3
--sopc_directory=c:/altera/61/quartus/sopc_builder
--sopc_lib_path=C:/Documents and
Settings/yaNGz/Desktop/NiosII_On_UP3+C:/altera/72sp2/ip/pci_express_compiler/lib/sopc_builder+C:/altera/72sp2/ip/ddr3_high_perf/lib/sopc_builder+C:/altera/72sp2/ip/ddr2_high_perf/lib/sopc_builder+C:/altera/72sp2/ip/ddr_high_perf/lib/sopc_builder+C:/altera/72sp2/ip/sopc_builder_ip+C:/altera/72sp2/ip/nios2_ip+C:/altera/72sp2/ip/triple_speed_ethernet/lib/sopc_builder+C:/altera/72sp2/ip/pci_compiler/lib/sopc_builder+C:/altera/72sp2/ip/ddr_ddr2_sdram/lib/sopc_builder+c:/altera/kits/nios/components+c:/altera/61/quartus/sopc_builder/components
--generate=1 --verbose=0 --software_only=0
--module_lib_dir=C:/altera/72sp2/ip/nios2_ip/altera_nios2
--sopc_quartus_dir=c:/altera/61/quartus/
--projectname=nios2_in_up3.quartus'
Error in processing. System NOT successfully generated.

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(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

It appears that you have the 6.1 and 7.2 releases mixed together. Quartus and
Nios II EDS need to have the same version.

BTW, you can better support for these sorts of issues from the Nios II Forum
at:
www.niosforum.com

+james+
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