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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
baud rate devisor - modeonz007 - Apr 22 6:02:08 2008
i am using spartan 3e ...i try to communicate with the pc by using
serial communication ..... i use 50 mhz clk ..... i want to get 9600
baud rate to send a 8 bit register .... what is the value of the
divisor should i take ..... i used 5208 for the divisor also i tried
1302 but i don't recive anything at the hyberterminal ?!!!!!! what
should i do
i made this code
c is the 50mhz clock
y is the tx
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY cout IS
PORT(
c : IN std_logic;
rst : IN std_logic;
y : OUT std_logic
);
-- Declarations
END cout ;
-- hds interface_end
ARCHITECTURE muha OF cout IS
signal tm:std_logic_vector(15 downto 0):=(others=>'0');
constant div:integer:=5208;
signal clk:std_logic;
signal busy:std_logic:='0';
signal mess:std_logic_vector(9 downto 0) :=(others=>'0');
signal cout:std_logic_vector(15 downto 0 ):=(others=>'0');
BEGIN
clkgen:process(rst,c)
begin
if rst='1' then
tm<=( others=>'0') ;
clk<='0';
elsif c='1' then
clk<='0';
if tm=div then
tm<=(others=>'0');
clk<='1';
else
tm<= tm + 1;
end if ;
end if ;
end process;
shif:process(c)
begin
if busy='0' then
mess<="0111010111";
busy<='1';
elsif ( busy='1' ) then
if (clk='1'and c='1') then
y<=mess(9);
mess(9 downto 1)<=mess(8 downto 0 );
cout<=cout + 1;
end if;
end if;
if cout=20 then
busy<='0';
cout<=(others=>'0');
end if;
end process;
END muha;
------------------------------------
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Re: baud rate devisor - John Kent - Apr 22 6:23:44 2008
Try indenting your code. It makes it easier to read.
It might have lost it's formatting when you pasted it perhaps.
How many clock cycles are required per bit ?
Usually the RX baud clock is 16 times the bit rate,
but there was a miniUART from opencores.org that used 4 clock cycles per
bit.
Check your UART design.
John.
modeonz007 wrote:
> i am using spartan 3e ...i try to communicate with the pc by using
> serial communication ..... i use 50 mhz clk ..... i want to get 9600
> baud rate to send a 8 bit register .... what is the value of the
> divisor should i take ..... i used 5208 for the divisor also i tried
> 1302 but i don't recive anything at the hyberterminal ?!!!!!! what
> should i do
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
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It might have lost it's formatting when you pasted it perhaps.
How many clock cycles are required per bit ?
Usually the RX baud clock is 16 times the bit rate,
but there was a miniUART from opencores.org that used 4 clock cycles per
bit.
Check your UART design.
John.
modeonz007 wrote:
> i am using spartan 3e ...i try to communicate with the pc by using
> serial communication ..... i use 50 mhz clk ..... i want to get 9600
> baud rate to send a 8 bit register .... what is the value of the
> divisor should i take ..... i used 5208 for the divisor also i tried
> 1302 but i don't recive anything at the hyberterminal ?!!!!!! what
> should i do
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
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Re: baud rate devisor - John Kent - Apr 22 6:43:59 2008
Try using clk'event or "rising_edge" for registering outputs
if rst = '1' then
count <= (others=>'0'); -- asynchronous reset
elsif rising_edge(clk) then
-- or:
-- elsif clk'event and clk='1' then
--
if count = MAX_COUNT then
count <= (others=>'0');
else
count <= count + 1;
end if;
end if;
John Kent wrote:
> Try indenting your code. It makes it easier to read.
> It might have lost it's formatting when you pasted it perhaps.
> How many clock cycles are required per bit ?
> Usually the RX baud clock is 16 times the bit rate,
> but there was a miniUART from opencores.org that used 4 clock cycles per
> bit.
> Check your UART design.
>
> John.
>
> modeonz007 wrote:
>
>> i am using spartan 3e ...i try to communicate with the pc by using
>> serial communication ..... i use 50 mhz clk ..... i want to get 9600
>> baud rate to send a 8 bit register .... what is the value of the
>> divisor should i take ..... i used 5208 for the divisor also i tried
>> 1302 but i don't recive anything at the hyberterminal ?!!!!!! what
>> should i do
>>
>>
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
if rst = '1' then
count <= (others=>'0'); -- asynchronous reset
elsif rising_edge(clk) then
-- or:
-- elsif clk'event and clk='1' then
--
if count = MAX_COUNT then
count <= (others=>'0');
else
count <= count + 1;
end if;
end if;
John Kent wrote:
> Try indenting your code. It makes it easier to read.
> It might have lost it's formatting when you pasted it perhaps.
> How many clock cycles are required per bit ?
> Usually the RX baud clock is 16 times the bit rate,
> but there was a miniUART from opencores.org that used 4 clock cycles per
> bit.
> Check your UART design.
>
> John.
>
> modeonz007 wrote:
>
>> i am using spartan 3e ...i try to communicate with the pc by using
>> serial communication ..... i use 50 mhz clk ..... i want to get 9600
>> baud rate to send a 8 bit register .... what is the value of the
>> divisor should i take ..... i used 5208 for the divisor also i tried
>> 1302 but i don't recive anything at the hyberterminal ?!!!!!! what
>> should i do
>>
>>
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
RE: baud rate devisor - tech...@tte-systems.com - Apr 27 6:47:28 2008
Hi,
Not sure if you are aware but there is a free tool (RapidiTTy FPGA Lite
v1.0) that provides a MIPS softcore and has a UART peripheral on it. You can
configure the required baudrate easily through the C file.
It also supports the Spartan3E development board from Digilent.
You can get this from http://www.tte-systems.com/download_list.php.
Best wishes.
_____
From: f...@yahoogroups.com [mailto:f...@yahoogroups.com] On Behalf
Of modeonz007
Sent: 07 April 2008 17:52
To: f...@yahoogroups.com
Subject: [fpga-cpu] baud rate devisor
i am using spartan 3e ...i try to communicate with the pc by using
serial communication ..... i use 50 mhz clk ..... i want to get 9600
baud rate to send a 8 bit register .... what is the value of the
divisor should i take ..... i used 5208 for the divisor also i tried
1302 but i don't recive anything at the hyberterminal ?!!!!!! what
should i do
i made this code
c is the 50mhz clock
y is the tx
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY cout IS
PORT(
c : IN std_logic;
rst : IN std_logic;
y : OUT std_logic
);
-- Declarations
END cout ;
-- hds interface_end
ARCHITECTURE muha OF cout IS
signal tm:std_logic_vector(15 downto 0):=(others=>'0');
constant div:integer:=5208;
signal clk:std_logic;
signal busy:std_logic:='0';
signal mess:std_logic_vector(9 downto 0) :=(others=>'0');
signal cout:std_logic_vector(15 downto 0 ):=(others=>'0');
BEGIN
clkgen:process(rst,c)
begin
if rst='1' then
tm<=( others=>'0') ;
clk<='0';
elsif c='1' then
clk<='0';
if tm=div then
tm<=(others=>'0');
clk<='1';
else
tm<= tm + 1;
end if ;
end if ;
end process;
shif:process(c)
begin
if busy='0' then
mess<="0111010111";
busy<='1';
elsif ( busy='1' ) then
if (clk='1'and c='1') then
y<=mess(9);
mess(9 downto 1)<=mess(8 downto 0 );
cout<=cout + 1;
end if;
end if;
if cout=20 then
busy<='0';
cout<=(others=>'0');
end if;
end process;
END muha;
[Non-text portions of this message have been removed]
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Not sure if you are aware but there is a free tool (RapidiTTy FPGA Lite
v1.0) that provides a MIPS softcore and has a UART peripheral on it. You can
configure the required baudrate easily through the C file.
It also supports the Spartan3E development board from Digilent.
You can get this from http://www.tte-systems.com/download_list.php.
Best wishes.
_____
From: f...@yahoogroups.com [mailto:f...@yahoogroups.com] On Behalf
Of modeonz007
Sent: 07 April 2008 17:52
To: f...@yahoogroups.com
Subject: [fpga-cpu] baud rate devisor
i am using spartan 3e ...i try to communicate with the pc by using
serial communication ..... i use 50 mhz clk ..... i want to get 9600
baud rate to send a 8 bit register .... what is the value of the
divisor should i take ..... i used 5208 for the divisor also i tried
1302 but i don't recive anything at the hyberterminal ?!!!!!! what
should i do
i made this code
c is the 50mhz clock
y is the tx
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY cout IS
PORT(
c : IN std_logic;
rst : IN std_logic;
y : OUT std_logic
);
-- Declarations
END cout ;
-- hds interface_end
ARCHITECTURE muha OF cout IS
signal tm:std_logic_vector(15 downto 0):=(others=>'0');
constant div:integer:=5208;
signal clk:std_logic;
signal busy:std_logic:='0';
signal mess:std_logic_vector(9 downto 0) :=(others=>'0');
signal cout:std_logic_vector(15 downto 0 ):=(others=>'0');
BEGIN
clkgen:process(rst,c)
begin
if rst='1' then
tm<=( others=>'0') ;
clk<='0';
elsif c='1' then
clk<='0';
if tm=div then
tm<=(others=>'0');
clk<='1';
else
tm<= tm + 1;
end if ;
end if ;
end process;
shif:process(c)
begin
if busy='0' then
mess<="0111010111";
busy<='1';
elsif ( busy='1' ) then
if (clk='1'and c='1') then
y<=mess(9);
mess(9 downto 1)<=mess(8 downto 0 );
cout<=cout + 1;
end if;
end if;
if cout=20 then
busy<='0';
cout<=(others=>'0');
end if;
end process;
END muha;
[Non-text portions of this message have been removed]
------------------------------------
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To unsubscribe, send a blank message to: f...@yahoogroups.com
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Re: baud rate divisor - John Kent - Apr 27 12:09:52 2008
Sounds cool,
I was playing with a very simple 8 instruction 16 bit micro the other day,
updating the design a bit:
http://members.optushome.com.au/jekent/Micro16/index.html
The project file is for the Spartan 3 starter board, but it should be
a simple matter of re-assigning the pins in the UCF file for the
Spartan 3E board.
It only uses about 13% of a XC3S200 and runs out of 3 x 4KBit
block RAMs. You should be able to extend the address bus by 2 bits
fairly easily so that it can use 16KBit block RAMs. It appears to run
happily at 50 MHz on the 200K gate Spartan 3.
It's a fairly simple design, so should be good as an introductory
educational design.
It should be possible to build a 4 x 5 array of these CPUs in a XC3S500E.
Perhaps if I added a multiply instruction they could perform a Fourier
butterfly each.
John.
t...@tte-systems.com wrote:
> Hi,
>
> Not sure if you are aware but there is a free tool (RapidiTTy FPGA Lite
> v1.0) that provides a MIPS softcore and has a UART peripheral on it. You can
> configure the required baudrate easily through the C file.
>
> It also supports the Spartan3E development board from Digilent.
>
> You can get this from http://www.tte-systems.com/download_list.php.
>
> Best wishes.
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
I was playing with a very simple 8 instruction 16 bit micro the other day,
updating the design a bit:
http://members.optushome.com.au/jekent/Micro16/index.html
The project file is for the Spartan 3 starter board, but it should be
a simple matter of re-assigning the pins in the UCF file for the
Spartan 3E board.
It only uses about 13% of a XC3S200 and runs out of 3 x 4KBit
block RAMs. You should be able to extend the address bus by 2 bits
fairly easily so that it can use 16KBit block RAMs. It appears to run
happily at 50 MHz on the 200K gate Spartan 3.
It's a fairly simple design, so should be good as an introductory
educational design.
It should be possible to build a 4 x 5 array of these CPUs in a XC3S500E.
Perhaps if I added a multiply instruction they could perform a Fourier
butterfly each.
John.
t...@tte-systems.com wrote:
> Hi,
>
> Not sure if you are aware but there is a free tool (RapidiTTy FPGA Lite
> v1.0) that provides a MIPS softcore and has a UART peripheral on it. You can
> configure the required baudrate easily through the C file.
>
> It also supports the Spartan3E development board from Digilent.
>
> You can get this from http://www.tte-systems.com/download_list.php.
>
> Best wishes.
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: baud rate divisor - rtstofer - Apr 30 14:01:04 2008
--- In f...@yahoogroups.com, John Kent wrote:
>
> Sounds cool,
>
> I was playing with a very simple 8 instruction 16 bit micro the
other day,
> updating the design a bit:
>
> http://members.optushome.com.au/jekent/Micro16/index.html
>
> The project file is for the Spartan 3 starter board, but it should be
> a simple matter of re-assigning the pins in the UCF file for the
> Spartan 3E board.
>
> It only uses about 13% of a XC3S200 and runs out of 3 x 4KBit
> block RAMs. You should be able to extend the address bus by 2 bits
> fairly easily so that it can use 16KBit block RAMs. It appears to run
> happily at 50 MHz on the 200K gate Spartan 3.
>
> It's a fairly simple design, so should be good as an introductory
> educational design.
>
> It should be possible to build a 4 x 5 array of these CPUs in a
XC3S500E.
> Perhaps if I added a multiply instruction they could perform a Fourier
> butterfly each.
>
> John.
>
John,
I really like your Micro16 project. I don't have an application at
the moment (summer is coming and it is time to play with boats) but I
am thinking that it would be a nice embedded controller for those
times where it seems like too much effort to create a state machine.
Thanks for the link!
Richard
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
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>
> Sounds cool,
>
> I was playing with a very simple 8 instruction 16 bit micro the
other day,
> updating the design a bit:
>
> http://members.optushome.com.au/jekent/Micro16/index.html
>
> The project file is for the Spartan 3 starter board, but it should be
> a simple matter of re-assigning the pins in the UCF file for the
> Spartan 3E board.
>
> It only uses about 13% of a XC3S200 and runs out of 3 x 4KBit
> block RAMs. You should be able to extend the address bus by 2 bits
> fairly easily so that it can use 16KBit block RAMs. It appears to run
> happily at 50 MHz on the 200K gate Spartan 3.
>
> It's a fairly simple design, so should be good as an introductory
> educational design.
>
> It should be possible to build a 4 x 5 array of these CPUs in a
XC3S500E.
> Perhaps if I added a multiply instruction they could perform a Fourier
> butterfly each.
>
> John.
>
John,
I really like your Micro16 project. I don't have an application at
the moment (summer is coming and it is time to play with boats) but I
am thinking that it would be a nice embedded controller for those
times where it seems like too much effort to create a state machine.
Thanks for the link!
Richard
------------------------------------
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To unsubscribe, send a blank message to: f...@yahoogroups.com
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Micro16 - John Kent - May 1 12:17:33 2008
Hi Richard,
Yes, it was originally intended as a replacement for a state machine to
read a compact flash card.
In the latest version I'm currently working on, I've combined the RTS
(Return from Subroutine)
and RTI (Return from Interrupt) instructions, reordered the opcodes, and
added a multiply instruction.
The CPU alone now uses about 9% of a XC3S200. With the UART, Timer and
I/O port it's about
18%. I haven't posted this version yet.
It may slow the CPU down, but I'm wondering if I should turn the JSR
instruction into a vectored
Software Interrupt. i.e. push the condition codes and the accumulator as
well as the return PC.
The RTS would simply skip over the accumulator and condition codes,
while the RTI would pop them.
I can't remember why I wanted to do that but I think it might have had
something to do with the ability
to set break points in the code. There are complications in implementing
break points because you don't
have access to the stack pointer so you have to do tricks like scan for
a particular return address to find
the bottom of the stack.
I'm trying to design a cross point data switch for it so I can build an
array of these cores.
I spent a day or two trying to work out a parallel data switch, but got
in a confused mess.
I need to tackle it in sections rather than trying to do the whole lot
at once.
I need an I/O port with handshaking, which I might make serial rather
than parallel,
a multi-port arbitrator, and a cross point switch.
This are more important things I should be working on at the moment, so
I might have to take
a break from it.
John.
>
> John,
>
> I really like your Micro16 project. I don't have an application at
> the moment (summer is coming and it is time to play with boats) but I
> am thinking that it would be a nice embedded controller for those
> times where it seems like too much effort to create a state machine.
>
> Thanks for the link!
>
> Richard
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Yes, it was originally intended as a replacement for a state machine to
read a compact flash card.
In the latest version I'm currently working on, I've combined the RTS
(Return from Subroutine)
and RTI (Return from Interrupt) instructions, reordered the opcodes, and
added a multiply instruction.
The CPU alone now uses about 9% of a XC3S200. With the UART, Timer and
I/O port it's about
18%. I haven't posted this version yet.
It may slow the CPU down, but I'm wondering if I should turn the JSR
instruction into a vectored
Software Interrupt. i.e. push the condition codes and the accumulator as
well as the return PC.
The RTS would simply skip over the accumulator and condition codes,
while the RTI would pop them.
I can't remember why I wanted to do that but I think it might have had
something to do with the ability
to set break points in the code. There are complications in implementing
break points because you don't
have access to the stack pointer so you have to do tricks like scan for
a particular return address to find
the bottom of the stack.
I'm trying to design a cross point data switch for it so I can build an
array of these cores.
I spent a day or two trying to work out a parallel data switch, but got
in a confused mess.
I need to tackle it in sections rather than trying to do the whole lot
at once.
I need an I/O port with handshaking, which I might make serial rather
than parallel,
a multi-port arbitrator, and a cross point switch.
This are more important things I should be working on at the moment, so
I might have to take
a break from it.
John.
>
> John,
>
> I really like your Micro16 project. I don't have an application at
> the moment (summer is coming and it is time to play with boats) but I
> am thinking that it would be a nice embedded controller for those
> times where it seems like too much effort to create a state machine.
>
> Thanks for the link!
>
> Richard
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )