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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Design mini cpu? - potxoka3a - Mar 25 7:25:30 2009
hi
I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA=
with VHDL, analyzing and changing a few signs of a data bus of 20 signals =
(transceiver). These signals often change protocol, as the team changes dur=
ing the design in VHDL I changed 2 times.
To avoid having to always fpga programming, thought if there was any way to=
change the interpretation of these signals. My PCB has a flash memory to b=
e managed from the FPGA, which currently do not use, but not how. Thought t=
o implement a CPU in the FPGA and program it in flash memory, but know how =
to do this. Or some sort of an interpreter to read the flash and the second=
, change the drive and how to interpret the data bus. So only have to updat=
e the flash memory can remotely do this :-D. I=C2=B4m new to this and that =
is why I ask help, can you guide?. thank you very much.
greetings
Antony
------------------------------------
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I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA=
with VHDL, analyzing and changing a few signs of a data bus of 20 signals =
(transceiver). These signals often change protocol, as the team changes dur=
ing the design in VHDL I changed 2 times.
To avoid having to always fpga programming, thought if there was any way to=
change the interpretation of these signals. My PCB has a flash memory to b=
e managed from the FPGA, which currently do not use, but not how. Thought t=
o implement a CPU in the FPGA and program it in flash memory, but know how =
to do this. Or some sort of an interpreter to read the flash and the second=
, change the drive and how to interpret the data bus. So only have to updat=
e the flash memory can remotely do this :-D. I=C2=B4m new to this and that =
is why I ask help, can you guide?. thank you very much.
greetings
Antony
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Design mini cpu? - Luke Teyssier - Mar 26 8:49:59 2009
--- In f...@yahoogroups.com, "potxoka3a" wrote:
>
> hi
>=20
> I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FP=
GA with VHDL, analyzing and changing a few signs of a data bus of 20 signal=
s (transceiver). These signals often change protocol, as the team changes d=
uring the design in VHDL I changed 2 times.
>=20
> To avoid having to always fpga programming, thought if there was any way =
to change the interpretation of these signals. My PCB has a flash memory to=
be managed from the FPGA, which currently do not use, but not how. Thought=
to implement a CPU in the FPGA and program it in flash memory, but know ho=
w to do this. Or some sort of an interpreter to read the flash and the seco=
nd, change the drive and how to interpret the data bus. So only have to upd=
ate the flash memory can remotely do this :-D. I=C2=B4m new to this and tha=
t is why I ask help, can you guide?. thank you very much.
>=20
> greetings
> Antony
>
Hello Anthony,
I had some trouble understanding your question, but let me try:
It sounds like you have a flash memory, an FPGA, a device that the HW team =
is designing while they are building it, and a HW team that can't make up i=
ts mind.
I don't advise adding a CPU unless you need it for something else. It will =
just make your life more complicated. If you really want a CPU, Xilinx has =
pico-blaze/micro-blaze, and Altera has Nios. See their websites.
You could implement a simple state machine that reads configuration words f=
rom flash, store it in a register, and use the output of that register to c=
onfigure signal muxes - a programmable one-way crosspoint switch.
L
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>
> hi
>=20
> I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FP=
GA with VHDL, analyzing and changing a few signs of a data bus of 20 signal=
s (transceiver). These signals often change protocol, as the team changes d=
uring the design in VHDL I changed 2 times.
>=20
> To avoid having to always fpga programming, thought if there was any way =
to change the interpretation of these signals. My PCB has a flash memory to=
be managed from the FPGA, which currently do not use, but not how. Thought=
to implement a CPU in the FPGA and program it in flash memory, but know ho=
w to do this. Or some sort of an interpreter to read the flash and the seco=
nd, change the drive and how to interpret the data bus. So only have to upd=
ate the flash memory can remotely do this :-D. I=C2=B4m new to this and tha=
t is why I ask help, can you guide?. thank you very much.
>=20
> greetings
> Antony
>
Hello Anthony,
I had some trouble understanding your question, but let me try:
It sounds like you have a flash memory, an FPGA, a device that the HW team =
is designing while they are building it, and a HW team that can't make up i=
ts mind.
I don't advise adding a CPU unless you need it for something else. It will =
just make your life more complicated. If you really want a CPU, Xilinx has =
pico-blaze/micro-blaze, and Altera has Nios. See their websites.
You could implement a simple state machine that reads configuration words f=
rom flash, store it in a register, and use the output of that register to c=
onfigure signal muxes - a programmable one-way crosspoint switch.
L
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Design mini cpu? - potxoka3a - Apr 1 16:40:30 2009
=09
hi
Thanks for answering ;-).
The problem is that I am a newbie with VHDL and know how to do this. I have=
a design that has 8 data lines and 6 control, basically according to contr=
ol signals, data about changes in the data bus and a control signal changes=
, but in the future may need to change the value data bus, and another is t=
he value of the control signals other than original.Habia thought the mini-=
cpu to store a binary program (spi external memory) to change this to be mo=
re flexible updates.
Not know if I can get VHDL values from memory and checks the data bus and, =
if true, put other data on the bus, reading the SPI memory. could make a st=
ructure and make a determination, but for example if I have scheduled to ta=
ke the memory of two possible values for tests and three are in the future?=
. I know how to do it in C, but not know to what extent can be done in VHDL=
. Thank you very much.
Greetings
Antony
--- In f...@yahoogroups.com, "Luke Teyssier" wrote:
>
> --- In f...@yahoogroups.com, "potxoka3a" wrote:
> >
> > hi
> >=20
> > I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an =
FPGA with VHDL, analyzing and changing a few signs of a data bus of 20 sign=
als (transceiver). These signals often change protocol, as the team changes=
during the design in VHDL I changed 2 times.
> >=20
> > To avoid having to always fpga programming, thought if there was any wa=
y to change the interpretation of these signals. My PCB has a flash memory =
to be managed from the FPGA, which currently do not use, but not how. Thoug=
ht to implement a CPU in the FPGA and program it in flash memory, but know =
how to do this. Or some sort of an interpreter to read the flash and the se=
cond, change the drive and how to interpret the data bus. So only have to u=
pdate the flash memory can remotely do this :-D. I=C2=B4m new to this and t=
hat is why I ask help, can you guide?. thank you very much.
> >=20
> > greetings
> > Antony
> >
>=20
> Hello Anthony,
>=20
> I had some trouble understanding your question, but let me try:
> It sounds like you have a flash memory, an FPGA, a device that the HW tea=
m is designing while they are building it, and a HW team that can't make up=
its mind.
>=20
> I don't advise adding a CPU unless you need it for something else. It wil=
l just make your life more complicated. If you really want a CPU, Xilinx ha=
s pico-blaze/micro-blaze, and Altera has Nios. See their websites.
>=20
> You could implement a simple state machine that reads configuration words=
from flash, store it in a register, and use the output of that register to=
configure signal muxes - a programmable one-way crosspoint switch.
>=20
> L
>
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
hi
Thanks for answering ;-).
The problem is that I am a newbie with VHDL and know how to do this. I have=
a design that has 8 data lines and 6 control, basically according to contr=
ol signals, data about changes in the data bus and a control signal changes=
, but in the future may need to change the value data bus, and another is t=
he value of the control signals other than original.Habia thought the mini-=
cpu to store a binary program (spi external memory) to change this to be mo=
re flexible updates.
Not know if I can get VHDL values from memory and checks the data bus and, =
if true, put other data on the bus, reading the SPI memory. could make a st=
ructure and make a determination, but for example if I have scheduled to ta=
ke the memory of two possible values for tests and three are in the future?=
. I know how to do it in C, but not know to what extent can be done in VHDL=
. Thank you very much.
Greetings
Antony
--- In f...@yahoogroups.com, "Luke Teyssier"
>
> --- In f...@yahoogroups.com, "potxoka3a"
> >
> > hi
> >=20
> > I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an =
FPGA with VHDL, analyzing and changing a few signs of a data bus of 20 sign=
als (transceiver). These signals often change protocol, as the team changes=
during the design in VHDL I changed 2 times.
> >=20
> > To avoid having to always fpga programming, thought if there was any wa=
y to change the interpretation of these signals. My PCB has a flash memory =
to be managed from the FPGA, which currently do not use, but not how. Thoug=
ht to implement a CPU in the FPGA and program it in flash memory, but know =
how to do this. Or some sort of an interpreter to read the flash and the se=
cond, change the drive and how to interpret the data bus. So only have to u=
pdate the flash memory can remotely do this :-D. I=C2=B4m new to this and t=
hat is why I ask help, can you guide?. thank you very much.
> >=20
> > greetings
> > Antony
> >
>=20
> Hello Anthony,
>=20
> I had some trouble understanding your question, but let me try:
> It sounds like you have a flash memory, an FPGA, a device that the HW tea=
m is designing while they are building it, and a HW team that can't make up=
its mind.
>=20
> I don't advise adding a CPU unless you need it for something else. It wil=
l just make your life more complicated. If you really want a CPU, Xilinx ha=
s pico-blaze/micro-blaze, and Altera has Nios. See their websites.
>=20
> You could implement a simple state machine that reads configuration words=
from flash, store it in a register, and use the output of that register to=
configure signal muxes - a programmable one-way crosspoint switch.
>=20
> L
>
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Design mini cpu? - rtstofer - Apr 2 14:35:50 2009
--- In f...@yahoogroups.com, "potxoka3a" wrote:
>
>
> hi
>
> Thanks for answering ;-).
>
> The problem is that I am a newbie with VHDL and know how to do this. I have a design that has 8 data lines and 6 control, basically according to control signals, data about changes in the data bus and a control signal changes, but in the future may need to change the value data bus, and another is the value of the control signals other than original.Habia thought the mini-cpu to store a binary program (spi external memory) to change this to be more flexible updates.
>
> Not know if I can get VHDL values from memory and checks the data bus and, if true, put other data on the bus, reading the SPI memory. could make a structure and make a determination, but for example if I have scheduled to take the memory of two possible values for tests and three are in the future?. I know how to do it in C, but not know to what extent can be done in VHDL. Thank you very much.
>
> Greetings
> Antony
VHDL is a hardware description language and not run-time executable in any sense. VHDL is used to define how hardware works in terms of registers, gates, state machines and things like that.
There are at least two approaches to modifying signals: build a hardware system that does the work with gate level logic or build a cpu of some type that can be programmed via some external gadget to do the same function.
It sounds like you want to have some combination of 6 control signals alter the value of 8 data signals in some manner that could change in the future. The problem seems to be that what each of the 64 possible control signals might mean in the future could be much different than what they mean right now.
Assuming there are no requirements to maintain some kind of state (where a modification might rely on previous data in the stream), I would tend to think of this as a ROM application. I would use all 8 data bits and the 6 control bits to address an 8 bit wide ROM that produced the required output bits. A 32kx8 EEPROM would work. It could also be pretty fast. It could be even faster if you copied the ROM to static RAM at startup. There is a lot of 10 nS RAM around.
You could probably design a tiny CPU to do the same thing by executing some kind of code from an SPI flash. The problem is that there is a huge number of things you could do to the data and you only want to select from a subset of 64 things. To design the cpu, I think you would have to be able to compute every possible modification of 8 bits (and that's a gigantic number) and I don't think this is going to be easy.
You can use your C code to generate the ROM contents quite easily.
If you can use a ROM, fine. Otherwise design a machine that loads RAM from ROM. In either event, use C to create the ROM contents.
Richard
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
>
>
> hi
>
> Thanks for answering ;-).
>
> The problem is that I am a newbie with VHDL and know how to do this. I have a design that has 8 data lines and 6 control, basically according to control signals, data about changes in the data bus and a control signal changes, but in the future may need to change the value data bus, and another is the value of the control signals other than original.Habia thought the mini-cpu to store a binary program (spi external memory) to change this to be more flexible updates.
>
> Not know if I can get VHDL values from memory and checks the data bus and, if true, put other data on the bus, reading the SPI memory. could make a structure and make a determination, but for example if I have scheduled to take the memory of two possible values for tests and three are in the future?. I know how to do it in C, but not know to what extent can be done in VHDL. Thank you very much.
>
> Greetings
> Antony
VHDL is a hardware description language and not run-time executable in any sense. VHDL is used to define how hardware works in terms of registers, gates, state machines and things like that.
There are at least two approaches to modifying signals: build a hardware system that does the work with gate level logic or build a cpu of some type that can be programmed via some external gadget to do the same function.
It sounds like you want to have some combination of 6 control signals alter the value of 8 data signals in some manner that could change in the future. The problem seems to be that what each of the 64 possible control signals might mean in the future could be much different than what they mean right now.
Assuming there are no requirements to maintain some kind of state (where a modification might rely on previous data in the stream), I would tend to think of this as a ROM application. I would use all 8 data bits and the 6 control bits to address an 8 bit wide ROM that produced the required output bits. A 32kx8 EEPROM would work. It could also be pretty fast. It could be even faster if you copied the ROM to static RAM at startup. There is a lot of 10 nS RAM around.
You could probably design a tiny CPU to do the same thing by executing some kind of code from an SPI flash. The problem is that there is a huge number of things you could do to the data and you only want to select from a subset of 64 things. To design the cpu, I think you would have to be able to compute every possible modification of 8 bits (and that's a gigantic number) and I don't think this is going to be easy.
You can use your C code to generate the ROM contents quite easily.
If you can use a ROM, fine. Otherwise design a machine that loads RAM from ROM. In either event, use C to create the ROM contents.
Richard
------------------------------------
To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com
______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.
(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )
Re: Design mini cpu? - Rick Collins - Apr 2 16:08:54 2009
--- In f...@yahoogroups.com, "rtstofer" wrote:
>
> --- In f...@yahoogroups.com, "potxoka3a" wrote:
> >
> >
> > hi
> >
> > Thanks for answering ;-).
> >
> > The problem is that I am a newbie with VHDL and know how to do this. I have a design that has 8 data lines and 6 control, basically according to control signals, data about changes in the data bus and a control signal changes, but in the future may need to change the value data bus, and another is the value of the control signals other than original.Habia thought the mini-cpu to store a binary program (spi external memory) to change this to be more flexible updates.
> >
> > Not know if I can get VHDL values from memory and checks the data bus and, if true, put other data on the bus, reading the SPI memory. could make a structure and make a determination, but for example if I have scheduled to take the memory of two possible values for tests and three are in the future?. I know how to do it in C, but not know to what extent can be done in VHDL. Thank you very much.
> >
> > Greetings
> > Antony
>
> VHDL is a hardware description language and not run-time executable in any sense. VHDL is used to define how hardware works in terms of registers, gates, state machines and things like that.
>
> There are at least two approaches to modifying signals: build a hardware system that does the work with gate level logic or build a cpu of some type that can be programmed via some external gadget to do the same function.
>
> It sounds like you want to have some combination of 6 control signals alter the value of 8 data signals in some manner that could change in the future. The problem seems to be that what each of the 64 possible control signals might mean in the future could be much different than what they mean right now.
>
> Assuming there are no requirements to maintain some kind of state (where a modification might rely on previous data in the stream), I would tend to think of this as a ROM application. I would use all 8 data bits and the 6 control bits to address an 8 bit wide ROM that produced the required output bits. A 32kx8 EEPROM would work. It could also be pretty fast. It could be even faster if you copied the ROM to static RAM at startup. There is a lot of 10 nS RAM around.
>
> You could probably design a tiny CPU to do the same thing by executing some kind of code from an SPI flash. The problem is that there is a huge number of things you could do to the data and you only want to select from a subset of 64 things. To design the cpu, I think you would have to be able to compute every possible modification of 8 bits (and that's a gigantic number) and I don't think this is going to be easy.
>
> You can use your C code to generate the ROM contents quite easily.
>
> If you can use a ROM, fine. Otherwise design a machine that loads RAM from ROM. In either event, use C to create the ROM contents.
I think what he may want is a table driven state machine. I guess I am thinking of something that will execute instructions from a table, like a CPU, but without the general purpose addressing and operators. It would just examine the inputs, one at a time, performing bit logical operations on the inputs and the data to determine the next state. The states would then produce outputs. Actually, the description is not clear, the 8 data lines may be the outputs.
This clearly is not a CPU in any real sense, but would take up much less space in the FPGA. Until he defines the requirements of the possible algorithms in more detail, there is not much more we could say. But this simple state machine would be able to implement any logic ladder function.
Rick
------------------------------------
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To unsubscribe, send a blank message to: f...@yahoogroups.com
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>
> --- In f...@yahoogroups.com, "potxoka3a"
> >
> >
> > hi
> >
> > Thanks for answering ;-).
> >
> > The problem is that I am a newbie with VHDL and know how to do this. I have a design that has 8 data lines and 6 control, basically according to control signals, data about changes in the data bus and a control signal changes, but in the future may need to change the value data bus, and another is the value of the control signals other than original.Habia thought the mini-cpu to store a binary program (spi external memory) to change this to be more flexible updates.
> >
> > Not know if I can get VHDL values from memory and checks the data bus and, if true, put other data on the bus, reading the SPI memory. could make a structure and make a determination, but for example if I have scheduled to take the memory of two possible values for tests and three are in the future?. I know how to do it in C, but not know to what extent can be done in VHDL. Thank you very much.
> >
> > Greetings
> > Antony
>
> VHDL is a hardware description language and not run-time executable in any sense. VHDL is used to define how hardware works in terms of registers, gates, state machines and things like that.
>
> There are at least two approaches to modifying signals: build a hardware system that does the work with gate level logic or build a cpu of some type that can be programmed via some external gadget to do the same function.
>
> It sounds like you want to have some combination of 6 control signals alter the value of 8 data signals in some manner that could change in the future. The problem seems to be that what each of the 64 possible control signals might mean in the future could be much different than what they mean right now.
>
> Assuming there are no requirements to maintain some kind of state (where a modification might rely on previous data in the stream), I would tend to think of this as a ROM application. I would use all 8 data bits and the 6 control bits to address an 8 bit wide ROM that produced the required output bits. A 32kx8 EEPROM would work. It could also be pretty fast. It could be even faster if you copied the ROM to static RAM at startup. There is a lot of 10 nS RAM around.
>
> You could probably design a tiny CPU to do the same thing by executing some kind of code from an SPI flash. The problem is that there is a huge number of things you could do to the data and you only want to select from a subset of 64 things. To design the cpu, I think you would have to be able to compute every possible modification of 8 bits (and that's a gigantic number) and I don't think this is going to be easy.
>
> You can use your C code to generate the ROM contents quite easily.
>
> If you can use a ROM, fine. Otherwise design a machine that loads RAM from ROM. In either event, use C to create the ROM contents.
I think what he may want is a table driven state machine. I guess I am thinking of something that will execute instructions from a table, like a CPU, but without the general purpose addressing and operators. It would just examine the inputs, one at a time, performing bit logical operations on the inputs and the data to determine the next state. The states would then produce outputs. Actually, the description is not clear, the 8 data lines may be the outputs.
This clearly is not a CPU in any real sense, but would take up much less space in the FPGA. Until he defines the requirements of the possible algorithms in more detail, there is not much more we could say. But this simple state machine would be able to implement any logic ladder function.
Rick
------------------------------------
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Re: Re: Design mini cpu? - Luke Teyssier - Apr 3 10:06:48 2009
Please go ahead and read a VHDL Tutorial. There are several: google VHDL Primer.
It will give you a much better idea what it can do and how hard it will be.
Luke
potxoka3a wrote:
>
> hi
>
> Thanks for answering ;-).
>
> The problem is that I am a newbie with VHDL and know how to do this. I
> have a design that has 8 data lines and 6 control, basically according
> to control signals, data about changes in the data bus and a control
> signal changes, but in the future may need to change the value data bus,
> and another is the value of the control signals other than
> original.Habia thought the mini-cpu to store a binary program (spi
> external memory) to change this to be more flexible updates.
>
> Not know if I can get VHDL values from memory and checks the data bus
> and, if true, put other data on the bus, reading the SPI memory. could
> make a structure and make a determination, but for example if I have
> scheduled to take the memory of two possible values for tests and three
> are in the future?. I know how to do it in C, but not know to what
> extent can be done in VHDL. Thank you very much.
>
> Greetings
> Antony
>
> --- In f...@yahoogroups.com,
> "Luke Teyssier" wrote:
>>
>> --- In f...@yahoogroups.com,
> "potxoka3a" wrote:
>> >
>> > hi
>> >
>> > I´m new to VHDL and FPGA. I´m currently doing a design in an FPGA
> with VHDL, analyzing and changing a few signs of a data bus of 20
> signals (transceiver). These signals often change protocol, as the team
> changes during the design in VHDL I changed 2 times.
>> >
>> > To avoid having to always fpga programming, thought if there was any
> way to change the interpretation of these signals. My PCB has a flash
> memory to be managed from the FPGA, which currently do not use, but not
> how. Thought to implement a CPU in the FPGA and program it in flash
> memory, but know how to do this. Or some sort of an interpreter to read
> the flash and the second, change the drive and how to interpret the data
> bus. So only have to update the flash memory can remotely do this :-D.
> I´m new to this and that is why I ask help, can you guide?. thank you
> very much.
>> >
>> > greetings
>> > Antony
>> >
>>
>> Hello Anthony,
>>
>> I had some trouble understanding your question, but let me try:
>> It sounds like you have a flash memory, an FPGA, a device that the HW
> team is designing while they are building it, and a HW team that can't
> make up its mind.
>>
>> I don't advise adding a CPU unless you need it for something else. It
> will just make your life more complicated. If you really want a CPU,
> Xilinx has pico-blaze/micro-blaze, and Altera has Nios. See their websites.
>>
>> You could implement a simple state machine that reads configuration
> words from flash, store it in a register, and use the output of that
> register to configure signal muxes - a programmable one-way crosspoint
> switch.
>>
>> L
>>
--
Luke Teyssier
Senior Staff Engineer
Cryptography Research, Inc.
575 Market St., 11th Floor
San Francisco, CA 94105
(415) 397-0123 x330 Direct
http://www.cryptography.com
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It will give you a much better idea what it can do and how hard it will be.
Luke
potxoka3a wrote:
>
> hi
>
> Thanks for answering ;-).
>
> The problem is that I am a newbie with VHDL and know how to do this. I
> have a design that has 8 data lines and 6 control, basically according
> to control signals, data about changes in the data bus and a control
> signal changes, but in the future may need to change the value data bus,
> and another is the value of the control signals other than
> original.Habia thought the mini-cpu to store a binary program (spi
> external memory) to change this to be more flexible updates.
>
> Not know if I can get VHDL values from memory and checks the data bus
> and, if true, put other data on the bus, reading the SPI memory. could
> make a structure and make a determination, but for example if I have
> scheduled to take the memory of two possible values for tests and three
> are in the future?. I know how to do it in C, but not know to what
> extent can be done in VHDL. Thank you very much.
>
> Greetings
> Antony
>
> --- In f...@yahoogroups.com
> "Luke Teyssier"
>>
>> --- In f...@yahoogroups.com
> "potxoka3a"
>> >
>> > hi
>> >
>> > I´m new to VHDL and FPGA. I´m currently doing a design in an FPGA
> with VHDL, analyzing and changing a few signs of a data bus of 20
> signals (transceiver). These signals often change protocol, as the team
> changes during the design in VHDL I changed 2 times.
>> >
>> > To avoid having to always fpga programming, thought if there was any
> way to change the interpretation of these signals. My PCB has a flash
> memory to be managed from the FPGA, which currently do not use, but not
> how. Thought to implement a CPU in the FPGA and program it in flash
> memory, but know how to do this. Or some sort of an interpreter to read
> the flash and the second, change the drive and how to interpret the data
> bus. So only have to update the flash memory can remotely do this :-D.
> I´m new to this and that is why I ask help, can you guide?. thank you
> very much.
>> >
>> > greetings
>> > Antony
>> >
>>
>> Hello Anthony,
>>
>> I had some trouble understanding your question, but let me try:
>> It sounds like you have a flash memory, an FPGA, a device that the HW
> team is designing while they are building it, and a HW team that can't
> make up its mind.
>>
>> I don't advise adding a CPU unless you need it for something else. It
> will just make your life more complicated. If you really want a CPU,
> Xilinx has pico-blaze/micro-blaze, and Altera has Nios. See their websites.
>>
>> You could implement a simple state machine that reads configuration
> words from flash, store it in a register, and use the output of that
> register to configure signal muxes - a programmable one-way crosspoint
> switch.
>>
>> L
>>
--
Luke Teyssier
Senior Staff Engineer
Cryptography Research, Inc.
575 Market St., 11th Floor
San Francisco, CA 94105
(415) 397-0123 x330 Direct
http://www.cryptography.com
------------------------------------
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