Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A

sir I have to design a CPU in VHDL . I have designed each block like alu,register,control,memory separately but i am not able to interface each . All block are working but all are isolated, Is the solution design a library & top package ? after that what to do ?

[Non-text portions of this message have been removed]

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Google is your friend - try "CPU design"

JK

abhishek kumar wrote:
> sir I have to design a CPU in VHDL . I have designed each block like alu,register,control,memory separately but i am not able to interface each . All block are working but all are isolated, Is the solution design a library & top package ? after that what to do ?
>
> [Non-text portions of this message have been removed]
>
> ------------------------------------
>
> To post a message, send it to: f...@yahoogroups.com
> To unsubscribe, send a blank message to: f...@yahoogroups.com

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

--- In f...@yahoogroups.com, "abhishek kumar" wrote:
>
> sir I have to design a CPU in VHDL . I have designed each block like alu,register,control,memory separately but i am not able to interface each . All block are working but all are isolated, Is the solution design a library & top package ? after that what to do ?
>
> [Non-text portions of this message have been removed]
>

Yes, you define a top level entity that has the signals required to connect to lower level entities together,

The top level also defines the device inputs and outputs and eventually a .ucf file defines the pinout.

The clock and reset signals, common to all entities, are created in the top entity.

Richard

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Your next step is to write unit tests for each block. No, not toy tests. Really,
test all the functionality and all the corners of each block. Expect to spend 4x
as much time and code testing each unit as you did to write it.

After that, do a google search on how CPUs are constructed and come back with
precise questions on how do do very specific focused things when you have
already tried and are stumped. Tell us what you have already done and why the
obvious isn't working.

You wouldn't want people to think you are just too lazy to look it up on google
and do your own work. ;-)

L

abhishek kumar wrote:
> sir I have to design a CPU in VHDL . I have designed each block like
> alu,register,control,memory separately but i am not able to interface
> each . All block are working but all are isolated, Is the solution
> design a library & top package ? after that what to do ?
>
> [Non-text portions of this message have been removed]

--
Luke Teyssier
Senior Staff Engineer
Cryptography Research, Inc.
575 Market St., 11th Floor
San Francisco, CA 94105
(415) 397-0123 x330 Direct
http://www.cryptography.com
------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Also,

Here is a good class you can access online:

http://www.engr.sjsu.edu/crabill/

L

abhishek kumar wrote:
> sir I have to design a CPU in VHDL . I have designed each block like
> alu,register,control,memory separately but i am not able to interface
> each . All block are working but all are isolated, Is the solution
> design a library & top package ? after that what to do ?
>
> [Non-text portions of this message have been removed]

--
Luke Teyssier
Senior Staff Engineer
Cryptography Research, Inc.
575 Market St., 11th Floor
San Francisco, CA 94105
(415) 397-0123 x330 Direct
http://www.cryptography.com
------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Hi Luke,

I worked at a government research organization back in the mid 1990s.
Alta Vista was the search engine of choice then. I remember one of my
colleagues (who had a PhD by the way) asking how he could determine if
two names he had were the same author. Simple I said .... put the name
into Alta Vista and see what web sites turned up. Sure enough the author
at one university had the same initials as the other name he was looking
up so the problem was solved. (I can't remember the exact details of
problem). But the point was that even people with doctorates hadn't
grasped the power of search engines or how they could be used.

Now I wasn't trying to be nasty suggesting Abhishek use a search
engineer. I did a few searches to see what I could find, and low and
behold there are wiki pages on CPU designs Micro architectures and all
sorts of stuff. There is even a link to an old web page with a block
diagram of how a CPU fits together, which I think is what Abishek is
looking for .... a data path model .... What he probably does not
appreciate is that he needs a sequencer or control section and that can
be the most complex part of the design.

My experience is with CISC computers using state machine and microcoded
sequencers. I have not tried to tackle a pipelined architecture yet, but
I guess that is the next step, so it's also a matter of determining what
type of architecture he wants to design. I assume it's a university
assignment so probably does not have to be very complex.

Anyway .... I should get on with my own study.

Cheers.

John.
Luke Teyssier wrote:
> Your next step is to write unit tests for each block. No, not toy tests. Really,
> test all the functionality and all the corners of each block. Expect to spend 4x
> as much time and code testing each unit as you did to write it.
>
> After that, do a google search on how CPUs are constructed and come back with
> precise questions on how do do very specific focused things when you have
> already tried and are stumped. Tell us what you have already done and why the
> obvious isn't working.
>
> You wouldn't want people to think you are just too lazy to look it up on google
> and do your own work. ;-)
>
> L
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

John Kent wrote:
> Hi Luke,
>
> I worked at a government research organization back in the mid 1990s.
> Alta Vista was the search engine of choice then. I remember one of my
> colleagues (who had a PhD by the way) asking how he could determine if
> two names he had were the same author. Simple I said .... put the name
> into Alta Vista and see what web sites turned up. Sure enough the author
> at one university had the same initials as the other name he was looking
> up so the problem was solved. (I can't remember the exact details of
> problem). But the point was that even people with doctorates hadn't
> grasped the power of search engines or how they could be used.
>
> Now I wasn't trying to be nasty suggesting Abhishek use a search
> engineer.
Search engine .... Freudian slip .... although he might have ended up
using a search engineer :-)
Get on with your work Johno !
> I did a few searches to see what I could find, and low and
> behold there are wiki pages on CPU designs Micro architectures and all
> sorts of stuff. There is even a link to an old web page with a block
> diagram of how a CPU fits together, which I think is what Abishek is
> looking for .... a data path model .... What he probably does not
> appreciate is that he needs a sequencer or control section and that can
> be the most complex part of the design.
>
> My experience is with CISC computers using state machine and microcoded
> sequencers. I have not tried to tackle a pipelined architecture yet, but
> I guess that is the next step,
Don't worry, if any RMIT colleagues are on this list wondering why I'm
not working on my literature survey, I don't plan to work on anything in
the next 2 years :-)

> so it's also a matter of determining what
> type of architecture he wants to design. I assume it's a university
> assignment so probably does not have to be very complex.
>
> Anyway .... I should get on with my own study.
>
> Cheers.
>
> John.
> Luke Teyssier wrote:
>
>> Your next step is to write unit tests for each block. No, not toy tests. Really,
>> test all the functionality and all the corners of each block. Expect to spend 4x
>> as much time and code testing each unit as you did to write it.
>>
>> After that, do a google search on how CPUs are constructed and come back with
>> precise questions on how do do very specific focused things when you have
>> already tried and are stumped. Tell us what you have already done and why the
>> obvious isn't working.
>>
>> You wouldn't want people to think you are just too lazy to look it up on google
>> and do your own work. ;-)
>>
>> L
>>
>>
>
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Has anyone ported Adam Dunkel's uIP TCP/IP stack to an FPGA processor ?

http://www.sics.se/~adam/uip/index.php/Main_Page

I have some demo code that is supposed to implement Adam's TCP/IP stack
in the cache memory of a PPC405 configured as an Ultra-Controller II on
a Virtex 4 board but it does not work. I was wanting to use the Virtex 4
board as an OFDM encoder/decoder for digital TV and use the ethernet
interface to pipe MPEG encoded video to and from the board. For MPEG
encoding I would need at least a XC3S1000 and even that might be a bit
small. If I used a Spartan 3 board I'd need a softcore CPU, although I
suppose the best solution would be to use EDK and the Microblaze. I
don't really have the time at the moment to spend working on it I suppose.

The problem with most low cost evaluation boards is that they only have
the one big SDRAM chip which is normally dedicated to the CPU, so using
them as frame stores for video processing is problematic. Frame stores
are needed for warping or transposition, or when you want to perform non
raster based operations. SDRAM is a real pain because it only really
achieves it's full bandwidth in burst mode which assumes linear
sequential addressing.

I'd also like to use the ethernet interface on a pair of Spartan 3E-500
boards for some computer vision experiments although they might be too
small for what I want to do and the S3E-500 board suffers from a lack of
separate SRAM for frame stores. The new Spartan 3 DSP board does have
one ZBT RAM that can be used as a frame store but there is only one of
them and it's limited to 1MByte.

The PPC405 has an APU interface, but do any softcore CPUs have a
provision for integrating things like video processing into them. There
is DMA I suppose, but can you use the ALU and address generator of a CPU
to perform video operations ?

John.

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Are you wanting to create a larger CPU entity that contains all your working
blocks and their interconnections using VHDL? I have simple tutorial for
modular design using VHDL here:

https://wiki.ittc.ku.edu/ittc/images/2/2b/EECS_140_modular_VHDL_Tutorial.pdf

It walks you through the process of declaring components and signals,
instantiating components and port mapping.

If you have constants being used all over your building blocks, you should
look into declaring them in a package.

~Jorge Ortiz
On Sat, Apr 4, 2009 at 6:08 AM, John Kent wrote:

> Google is your friend - try "CPU design"
>
> JK
> abhishek kumar wrote:
> > sir I have to design a CPU in VHDL . I have designed each block like
> alu,register,control,memory separately but i am not able to interface each .
> All block are working but all are isolated, Is the solution design a library
> & top package ? after that what to do ?
> >
> > [Non-text portions of this message have been removed]
> >
> >
> >
> > ------------------------------------
> >
> > To post a message, send it to: f...@yahoogroups.com
> > To unsubscribe, send a blank message to:
> f...@yahoogroups.comYahoo!
> Groups Links
> >
> >
> >
> >
> > --
> http://www.johnkent.com.au
> http://members.optushome.com.au/jekent
>
>
>
[Non-text portions of this message have been removed]

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Hi John,

On Sun, 2009-04-05 at 13:33 +1000, John Kent wrote:
> Has anyone ported Adam Dunkel's uIP TCP/IP stack to an FPGA
> processor ?
>
> http://www.sics.se/~adam/uip/index.php/Main_Page

one member of my team did this for our ECO32 processor, which
runs in a Xilinx XC3S1000 (mounted on XESS' XSA-3S1000 board).
It was rather easy to do and took only a few days. If you port
the stack, pay attention to define endianness correctly - we
didn't, and it was a pain to debug... ;-)

Hellwig

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

--- In f...@yahoogroups.com, John Kent wrote:
>
> Has anyone ported Adam Dunkel's uIP TCP/IP stack to an FPGA processor ?
> John.
>
> --
> http://www.johnkent.com.au
> http://members.optushome.com.au/jekent
>

John,

I can't help with very much on your project but I have used uIP on an ARM project. There is a uIP mailing list that may be helpful. I have forgotten how I signed up but it couldn't have been difficult. I get very little traffic from the list but there are some fairly knowledgeable folks.

One thing to consider with uIP is that it can only deal with one packet in flight. This is a problem with transmission because some receiving systems delay the ACK and uIP doesn't send the next packet until it receives the ACK. There have been discussions about this but I don't believe it has ever been resolved. In fact, I don't think it can be resolved in the context of uIP. The low memory footprint pretty much limits having multiple packets hanging around.

lwIP may be another choice. Again, this stack is by Adam Dunkel but it is much more sophisticated. When I looked at it, the documentation was sparse and I could deal with the issues in uIP.

My project was pretty simple: take a stream of 6 bit IBM 1627 Plotter commands coming in on SPI, accumulate the steps, convert the steps to HPGL commands and send the result to a networked LaserJet III. It works pretty well.

Richard

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Hi Hellwig,

I was wondering if your ECO32 processor had the TCP/IP stack running. I
did download the code a few months ago but I never got as far as
checking it out, which is a bit slack of me. Is it possible to graft
co-processors onto ECO32 ?

John.

Hellwig Geisse wrote:
> Hi John,
>
> On Sun, 2009-04-05 at 13:33 +1000, John Kent wrote:
>
>> Has anyone ported Adam Dunkel's uIP TCP/IP stack to an FPGA
>> processor ?
>>
>> http://www.sics.se/~adam/uip/index.php/Main_Page
>>
>
> one member of my team did this for our ECO32 processor, which
> runs in a Xilinx XC3S1000 (mounted on XESS' XSA-3S1000 board).
> It was rather easy to do and took only a few days. If you port
> the stack, pay attention to define endianness correctly - we
> didn't, and it was a pain to debug... ;-)
>
> Hellwig
>
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Hi Richard,

It does not surprise me that uIP has limited packet buffing capability.
OK on lwIP. The limitation in the PPC405 is the Instruction cache I
think. It's limited to 16 KB, 2-way set associative instruction cache
and the data cache is the same. So there is probably enough data space
for storing packets. The limitation is really keeping the program small
enough to fit in the instruction cache and still being able to handle
sequence number buffering.

OK on running the LaserJet III over the network. I'm a bit unclear on
what is generating the plotter commands though.

The Contiki 8bit micro windows system looked pretty cute. I remember
looking through the documentation for it and thinking it was pretty well
done. I was thinking that it would be nice to port it to System09 but
I'm not sure I want to be spending my valuable time developing software
for obsolete 8 bit microcomputers.

Hellwig's ECO32 is probably not a bad way to go on the Spartan 3
although for video processing the CPU may need to be redesigned from the
ground up to integrate co-processing engines.

John.

rtstofer wrote:
> John,
>
> I can't help with very much on your project but I have used uIP on an ARM project. There is a uIP mailing list that may be helpful. I have forgotten how I signed up but it couldn't have been difficult. I get very little traffic from the list but there are some fairly knowledgeable folks.
>
> One thing to consider with uIP is that it can only deal with one packet in flight. This is a problem with transmission because some receiving systems delay the ACK and uIP doesn't send the next packet until it receives the ACK. There have been discussions about this but I don't believe it has ever been resolved. In fact, I don't think it can be resolved in the context of uIP. The low memory footprint pretty much limits having multiple packets hanging around.
>
> lwIP may be another choice. Again, this stack is by Adam Dunkel but it is much more sophisticated. When I looked at it, the documentation was sparse and I could deal with the issues in uIP.
>
> My project was pretty simple: take a stream of 6 bit IBM 1627 Plotter commands coming in on SPI, accumulate the steps, convert the steps to HPGL commands and send the result to a networked LaserJet III. It works pretty well.
>
> Richard
>
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

John,

On Mon, 2009-04-06 at 16:18 +1000, John Kent wrote:

> Is it possible to graft co-processors onto ECO32 ?

this depends on what exactly you mean by "co-processor":
a) in MIPS terminology: some logic tightly coupled to the
CPU, with registers, and possibly interpreting instructions
taken off the instruction stream flowing into the CPU,
b) some on-chip logic realizing a "peripheral device", coupled
to the CPU by a bus, with or without external connections,
c) off-chip logic connected to some pins of the FPGA

I don't have a defined interface in the sense of a). But this
is an open design, and you could of course augment the CPU
with whatever co-processor you dream of... ;-)
The biggest hurdle here is the already crowded opcode space.

As the Xilinx FPGA doesn't support tri-state busses within
the chip, our on-chip bus controller is merely a big
multiplexer. It is of course possible to attach more
"peripherals" to it, which themselves could be programmable.
These "peripherals" could also be connected to real other
chips outside the FPGA, as is the case with our TCP/IP
implementation.

But: We don't have DMA yet. This would be nice to have,
especially for the IDE interface (the current solution
is to have a buffer in block RAM and the disk driver
copying the data from/to main memory as soon as the
IDE controller triggers an interrupt).

Hellwig

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

I was thinking in terms of logic tightly coupled to the CPU in order to
get data into and out of memory the most efficiently. Does your CPU
support caching ? If so what write back policy does the data cache use ?

To pick up on what Tommy Thorn was saying it looked like batching was
simply a way of scheduling graphics operations during the frame. To
support efficient memory access you have to read main memory into cache,
modify it then write it back.

John.
Hellwig Geisse wrote:
> John,
>
> On Mon, 2009-04-06 at 16:18 +1000, John Kent wrote:
>
>
>> Is it possible to graft co-processors onto ECO32 ?
>>
>
> this depends on what exactly you mean by "co-processor":
> a) in MIPS terminology: some logic tightly coupled to the
> CPU, with registers, and possibly interpreting instructions
> taken off the instruction stream flowing into the CPU,
> b) some on-chip logic realizing a "peripheral device", coupled
> to the CPU by a bus, with or without external connections,
> c) off-chip logic connected to some pins of the FPGA
>
> I don't have a defined interface in the sense of a). But this
> is an open design, and you could of course augment the CPU
> with whatever co-processor you dream of... ;-)
> The biggest hurdle here is the already crowded opcode space.
>
> As the Xilinx FPGA doesn't support tri-state busses within
> the chip, our on-chip bus controller is merely a big
> multiplexer. It is of course possible to attach more
> "peripherals" to it, which themselves could be programmable.
> These "peripherals" could also be connected to real other
> chips outside the FPGA, as is the case with our TCP/IP
> implementation.
>
> But: We don't have DMA yet. This would be nice to have,
> especially for the IDE interface (the current solution
> is to have a buffer in block RAM and the disk driver
> copying the data from/to main memory as soon as the
> IDE controller triggers an interrupt).
>
> Hellwig
>
> ------------------------------------
>
> To post a message, send it to: f...@yahoogroups.com
> To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

--- In f...@yahoogroups.com, John Kent wrote:
> OK on running the LaserJet III over the network. I'm a bit unclear on
> what is generating the plotter commands though.

The IBM 1130 had a CalComp drum plotter that IBM called the 1627 and they provided a library for driving it. Ordinarily, the plotter was added to the list of IO devices a program might use by having it included in the *IOCS job control card. The library was linked automatically.

The software would generate a 6 bit motion command for every step. The six bits represented PenUp, PenDown, +X step, -X step, +Y step, -Y step. So, about 3 bits were used for any given command.

These commands were sent out an IO port directly to the 1627 using an WXIO Write command. The plotter generated an interrupt when each command was complete and also provided Busy and Not Ready status bits when interrogated by an XIO Sense Device instruction.

So, in my emulation, I accept the 6 bits in the Plotter entity, convert them to 8 bits by padding and send them to my ARM gadget via SPI.

The ARM accumulates all steps when the pen is up and accumulates only identical steps when the pen is down. When the pen is commanded down or the type of step changes, the totalized pulse count is used to create an HPGL motion command string. This string is sent over my LAN to a print server and ultimately to the LaserJet III.

In the old days, every HP printer implemented HPGL. Nowadays, they seem to limit it to the higher performance printers. I wonder if my new multifunction (scanner, copier, FAX, printer) device implements it? Hm...

Richard

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

On Mon, 2009-04-06 at 22:05 +1000, John Kent wrote:
> I was thinking in terms of logic tightly coupled to the CPU in order
> to get data into and out of memory the most efficiently. Does your
> CPU support caching ?

No, I'm sorry, not yet. I know that this is crucial to
overcome the latency of both Flash and SDRAM memories.
I even had a student working on that, but he didn't
quite get through. So I will have to tackle this problem
personally, but because of other duties I won't start
with it before fall.

Hellwig

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Hello abhishek,
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 You s=
aid that, designed the necessary modules in separerty but cant interface al=
l in one. You can port map all modules using component declaration and inst=
antiation statements and use one global clock for interfacing.Your interfac=
ing should be in a=A0=A0data flow pattern and refer stuctural design topics=
in VHDL. Please refer VHDL by J.Bhasker and Digital design with VHDL by ve=
loni A. Petroni.=20
=A0=A0=A0=A0=A0=A0=A0 Thank you.=A0
Suresh

--- On Sat, 4/4/09, abhishek kumar wrote:
From: abhishek kumar
Subject: [fpga-cpu]
To: f...@yahoogroups.com
Date: Saturday, 4 April, 2009, 3:18 PM

sir I have to design a CPU in VHDL . I have designed each block like alu,re=
gister, control,memory separately but i am not able to interface each . All=
block are working but all are isolated, Is the solution design a library &=
amp; top package ? after that what to do ?

[Non-text portions of this message have been removed]

From Chandigarh to Chennai - find friends all over India. Go to http:=
//in.promos.yahoo.com/groups/citygroups/

[Non-text portions of this message have been removed]

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: fpga-cpu-unsubscribe@yahoogroups.c=
om



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

On Sat, 4 Apr 2009 12:07:01 -0500, you wrote:

>Are you wanting to create a larger CPU entity that contains all your working
>blocks and their interconnections using VHDL? I have simple tutorial for
>modular design using VHDL here:
>
>https://wiki.ittc.ku.edu/ittc/images/2/2b/EECS_140_modular_VHDL_Tutorial.pdf

There is what I think is at least one small error in that document. On
the 4th page in the VHDL implementation for an xor2 gate, the
ARCHITECTURE section assigns the behavioral expression to F. The
available signal in the ENTITY description is G and there is no other
SIGNAL statement present.

>It walks you through the process of declaring components and signals,
>instantiating components and port mapping.
>
>If you have constants being used all over your building blocks, you should
>look into declaring them in a package.
>
>~Jorge Ortiz

Jon
------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )

Ah yes... That should be:

*G* <= (A AND (NOT B)) OR ((NOT A) AND B);

Thanks for locating that typo.

~Jorge
On Mon, Apr 6, 2009 at 4:43 PM, Jon Kirwan wrote:

> On Sat, 4 Apr 2009 12:07:01 -0500, you wrote:
>
> >Are you wanting to create a larger CPU entity that contains all your
> working
> >blocks and their interconnections using VHDL? I have simple tutorial for
> >modular design using VHDL here:
> >
> >
> https://wiki.ittc.ku.edu/ittc/images/2/2b/EECS_140_modular_VHDL_Tutorial.pdf
>
> There is what I think is at least one small error in that document. On
> the 4th page in the VHDL implementation for an xor2 gate, the
> ARCHITECTURE section assigns the behavioral expression to F. The
> available signal in the ENTITY description is G and there is no other
> SIGNAL statement present.
>
> >It walks you through the process of declaring components and signals,
> >instantiating components and port mapping.
> >
> >If you have constants being used all over your building blocks, you should
> >look into declaring them in a package.
> >
> >~Jorge Ortiz
>
> Jon
>
>
[Non-text portions of this message have been removed]

------------------------------------

To post a message, send it to: f...@yahoogroups.com
To unsubscribe, send a blank message to: f...@yahoogroups.com



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )