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Discussion Groups | FPGA-CPU | Implementation of LRU algo in verilog


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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Implementation of LRU algo in verilog - ruchi_rastogi25 - Aug 2 4:08:35 2009

Hi all,
I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware.
Thanks,
Ruchi

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Re: Implementation of LRU algo in verilog - Hellwig Geisse - Aug 2 4:58:21 2009

Hi Ruchi,

On Sun, 2009-08-02 at 08:00 +0000, ruchi_rastogi25 wrote:

> I am designing a cache memory in verilog. I am facing problem in
> desiging LRU unit for set associative cache. Can anybody tell me what
> is the optimal way of implementating LRU(Least Recently Used)algo in
> Hardware.

in your application, is it absolutely necessary to implement
an exact LRU replacement scheme? Then the associativity of your
cache should be small. Otherwise you could approximate LRU, or
even use random replacement. I cite from Patterson & Hennessy:

"In practice, LRU is too costly to implement for hierarchies
with more than a small degree of associativity (two to four,
typically). [...] Even for four-way set associativity, LRU is
often approximated - for example, by keeping track of which of
a pair of blocks is LRU (which requires 1 bit), and then tracking
which block in each pair is LRU (which requires 1 bit per pair).
[...] Random replacement is simple to build in hardware, and
for a two-way set-associative cache, random replacement has
a miss rate about 1.1 times higher than LRU replacement. [...]
In fact, random replacement is sometimes better than simple LRU
approximations that can be easily implemented in hardware."

Hellwig

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