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Discussion Groups | FPGA-CPU | vhdl newbie question: multiply divide add

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

vhdl newbie question: multiply divide add - Sean Jensen_Grey - Mar 30 18:23:00 2001


I am trying to learn VHDL on my own and I have a couple questions I haven't been
able to answer.

In reviewing the pretty straightforward design of a forth cpu I have a question
about the code snippet:

http://www.ultratechnology.com/p16vhdl.htm

-- define the first mux in the diagram
with alu_sel select
alu_out <= (t xor n) when "01",
(t and n) when "10",
--> (t + n) when "11", <--
(not t) when others;

Does VHDL just construct an optimal adder for a vector of the bit length of t and
n?

What about when I see multiply and divide operators in VHDL code? Is there a
default architecture that is implemented? Would I have to make my own multiply
or divide unit if I wanted different behavior (optimize for speed or area)?

What controls what the adder, multiplier or divider logic is like in a
design?

I feel very comfortable with C/C++ as I know what the machine looks like
underneath and what the compiler emits from my code. For VHDL I am not as
comfortable with how VHDL -> RTL -> FPGA or gate synthesis occurs.

Here is a link to a Wallace Booth Multiplier.

http://mikro.e-technik.uni-ulm.de/vhdl/vhdl_models.html

Thanks, Sean.





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Re: vhdl newbie question: multiply divide add - Navendu Sinha - Mar 31 0:38:00 2001

-- define the first mux in the diagram
with alu_sel select
alu_out <= (t xor n) when "01",
(t and n) when "10",
--> (t + n) when "11", <--
(not t) when others;

Does VHDL just construct an optimal adder for a vector of the bit length of
t and
n?
Ans : VHDL synthesizer might pick up an adder from the library u are trying
to target. It may be optimum or it maynot be. For example, at lower bits
both CLA and ripple adder give nearly the same performance but at higher
speeds, CLA exceeds RC. The synthesizer, I think might be choosing the two
based on the constrainst that u give. If u give time optimization, then
obviously it should pick up a CLA, but if u give area i might pick up RC as
well. In any case, all synthesizers have complier directives by which u can
ask it tp pick up which kind of adder everytime it sees a "+". What about when I see multiply and divide operators in VHDL code? Is there a
default architecture that is implemented? Would I have to make my own
multiply
or divide unit if I wanted different behavior (optimize for speed or area)?

What controls what the adder, multiplier or divider logic is like in a
design?

Ans: The mmulitply and divide operators are synthesizeable only if the
library supports them. Be careful about such implementations anyway. A
muliplier or divider ckt. can be better made according to one's needs than
rely on the synthesizer's ability to generate a code for it. What I want to
say is that the HDL synthesizers are ultimatley tools, they best understand
simple constucts of h/w. It should be to the deisgner to deal with the one
level up abstraction, like DIV a nd MULT,
U can use these opeartors best in sumulation left and right withiut any
problem, not don't trust these with synthesis, it might not give u whhat u
wanted...
I feel very comfortable with C/C++ as I know what the machine looks like
underneath and what the compiler emits from my code. For VHDL I am not as
comfortable with how VHDL -> RTL -> FPGA or gate synthesis occurs.

Here is a link to a Wallace Booth Multiplier.





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Re: vhdl newbie question: multiply divide add - Author Unknown - Mar 31 6:36:00 2001

Hello.

Depending on the tool you are using, perhaps you will have to buy separate
licenses for the multipliers or dividers. For example, with Synopsys Design
Compiler.

If your synthesis tool can generate multipliers and dividers, you could
try it and then check if it covers your needs. If not, you will have to
design them yourself.

By the way, be carefull with one detail. In FPGAs things are not totally
like in pure design. For example, Xilinx FPGAs have carry resources
specially designed to speed up adders and multipliers. These carry
resources are implemented with true gates, not SRAM LUTs, so they are very
fast.

If you try a carry propagation adder of 16 bits and one CLA adder, for
example, it is likely that the propagation adder will be almost the same
speed. That is because the carry is propagated through dedicated hardware,
and the look-ahead logic is synthetized via LUTs. Well, at 32 bits Xilinx's
manuals say that the difference is still small, and the area is smaller.
Anyway, I think with 32 bits you could try another adder design.

Perhaps you could try some models of adders and multipliers at different
bit widths and post your results here, so we can discuss on them.

With best regards, Mike.

To:
From: Sean Jensen_Grey <>
Date sent: Fri, 30 Mar 2001 15:23:20 -0800 (PST)
Send reply to:
Subject: [fpga-cpu] vhdl newbie question: multiply divide add > I am trying to learn VHDL on my own and I have a couple questions I haven't been
> able to answer.
>
> In reviewing the pretty straightforward design of a forth cpu I have a question
> about the code snippet:
>
> http://www.ultratechnology.com/p16vhdl.htm
>
> -- define the first mux in the diagram
> with alu_sel select
> alu_out <= (t xor n) when "01",
> (t and n) when "10",
> --> (t + n) when "11", <--
> (not t) when others;
>
> Does VHDL just construct an optimal adder for a vector of the bit length of t and
> n?
>
> What about when I see multiply and divide operators in VHDL code? Is there a
> default architecture that is implemented? Would I have to make my own multiply
> or divide unit if I wanted different behavior (optimize for speed or area)?
>
> What controls what the adder, multiplier or divider logic is like in a
> design?
>
> I feel very comfortable with C/C++ as I know what the machine looks like
> underneath and what the compiler emits from my code. For VHDL I am not as
> comfortable with how VHDL -> RTL -> FPGA or gate synthesis occurs.
>
> Here is a link to a Wallace Booth Multiplier.
>
> http://mikro.e-technik.uni-ulm.de/vhdl/vhdl_models.html
>
> Thanks, Sean. >
> To Post a message, send it to:
> To Unsubscribe, send a blank message to:
>
>

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RE: vhdl newbie question: multiply divide add - Jan Gray - Apr 6 1:10:00 2001

> By the way, be carefull with one detail. In FPGAs things
> are not totally
> like in pure design. For example, Xilinx FPGAs have carry resources
> specially designed to speed up adders and multipliers. These carry
> resources are implemented with true gates, not SRAM LUTs, so they
> are very
> fast.
>
> If you try a carry propagation adder of 16 bits and one CLA
> adder, for
> example, it is likely that the propagation adder will be almost the same
> speed. That is because the carry is propagated through dedicated
> hardware,
> and the look-ahead logic is synthetized via LUTs. Well, at 32
> bits Xilinx's
> manuals say that the difference is still small, and the area is smaller.
> Anyway, I think with 32 bits you could try another adder design.

Exactly. See also Factoids in http://www.fpgacpu.org/log/oct00.html#001027.

Jan Gray, Gray Research LLC

______________________________
Stellaris® MCU Family: New Parts, New Package, New Price.


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