Sign in

username:

password:



Not a member?

Search fpga-cpu



Search tips

Subscribe to fpga-cpu



fpga-cpu by Keywords

Altera | CISCifying | IDE | ISA | Java | JHDL | JTAG | LBU | MicroBlaze | PAR | PCI | RISC | SoC | Spartan | Transputers | Verilog | VHDL | Virtex | VLIW | WebPack | Xilinx | Xsoc | YARD-1A

Ads

Discussion Groups

See Also

DSPFPGAElectronics

Discussion Groups | FPGA-CPU | Re: issue: xsoc\Xsoc.pdf generates "File does not begi n with %PDF-"

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Re: issue: xsoc\Xsoc.pdf generates "File does not begi n with %PDF-" - Hernan Dario Sanchez Echeverri - Mar 17 11:04:00 2000

Hi.

The xsoc/xsoc.pdf file is the control file of the "Xilinx Project Manager"
project. They use the same PDF extension. The real PDF files are in the
DOC directory.

For the encrypted PDF files, please install the patch for Ghostscript. You
can find it here:

http://www.ozemail.com.au/~geoffk/pdfencrypt/

And, by the way... nice work with the processor... Excelent!!!... some idea
doing this using VHDL ? I would like to help in any way.

Hernán Sánchez
Analista de Telecomunicaciones
SURATEP

> -----Mensaje original-----
> De: Dan Crowl [SMTP:]
> Enviado el: Jueves, 16 de Marzo de 2000 11:12 p.m.
> Para:
> Asunto: [fpga-cpu] issue: xsoc\Xsoc.pdf generates "File does not
> begin with %PDF-"
>
> Nice piece of work, Jan, thanks.
>
> trivial issues:
> a. Downloaded the distribution to NT4 system and installed, compiled and
> simulated the demos [no board yet] according to _Getting
> Started.._procedure with only one incident: "-Wl ignored" reported by
> lcc-xr16 on p.7, step 1.
>
> b. the file xsoc\xsoc.pdf appears as an Acrobat file, though it really
> isn't ( -- might confuse some):
>
> [project]
> name=xsoc
> netlist=d:\xsoc\xsoc\xsoc.alb
> contents=xsoc
> date=02/23/100
> time=10:44:48
> version=3.1.4.05.99q
> generics=MAX
> Type=XILINX8
> .
> .
> .
> c. Ghostview cannot read the \doc *.pdf files because it sees them as
> being
> encrypted.
>
> /Dan Crowl
> -------------------------------
> Daniel M Crowl
> RETICOM (541) 347-3413 >





(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )


XSOC in Verilog and perhaps VHDL - Jan Gray, Gray Research LLC - Mar 17 15:23:00 2000

> From: Hernan Dario Sanchez Echeverri [mailto:]

> some idea
> doing this using VHDL ? I would like to help in any way.

Thanks for your kind words and your interest.

There is a Verilog version of the XSOC Project, including xr16. It needs a
little more polish, documentation, and testing before I add it to the XSOC
Project Distribution. I hope to release it for beta testing approximately
April 1.

Assuming there was a Verilog version, would that be acceptable to you, or do
you have a requirement to use VHDL? How to people feel about Verilog vs.
VHDL? I am more fluent in Verilog (although still a newbie), than VHDL, and
prefer it to VHDL. I do understand there are some facilities in VHDL that
are missing in Verilog.

I am also looking forward to using a synthesis tool that supports RLOCs and
FMAPs. Unfortunately FPGA Express (provided in Xilinx Student Ed.) does not
(see http://www.fpgacpu.org/usenet/rope_pushing.html), and I have had to
resort to partial floorplanning through program generated UCF files.

For your interest here is a message comparing the schematic version to the
Verilog version.

<<<
From: Jan Gray
Sent: Wednesday, February 09, 2000 3:21 PM
Subject: ... comparing schematic to Verilog version

...
Now that we have the design running properly in Verilog, let's compare the
schematic to the Verilog+explicitly floorplanned registers version. Target
XC4005XLPC84C-3. Effort level 5/5 on both. Identical timing specs except
clock frequency goal.

What Sch'c Verilog
---- ----- -------
Cycle time 41 53 ns
Freq 24.5 18.9 MHz
Flops 252 252
4LUTs 263 288
ROMs 21 0
Total FGs 284 288
3LUTs 40 48
RAMs 64 64
TBUFs 152 152
P&R time 5'45" 8'52"

Commentary: here, the Verilog doesn't fare too badly. 25% slower,
approximately the same area. Of course, I took great care in coding the
Verilog, examining the output to make sure no extraneous logic was
introduced, and applied as much floorplanning as was practical (e.g.
registers and RAMs).
...
>>>

Jan Gray
Gray Research LLC



(You need to be a member of fpga-cpu -- send a blank email to fpga-cpu-subscribe@yahoogroups.com )