This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Hi, i needed one VHDL command which tells the folwing information. a <= (b and c) or (....).. if event occured on a, can we know due to which signals in the RHS side of the above example, event occured on a ?? please let me know. Thanks and regards appu ____________________________________________________________ |