This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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Here's a simple UART in JHDL that appears to work, both in jab and on my Insight XC2S100 board. This code is released under the GPL. Please distribute it, fix it, and revise it accordingly. I wrote it on my personal time and equipment at home. It's part of my xr16vx project. This is a 9600 baud UART that only samples at 4X the baud rate, and does no error checking or detection. Set CLKFREQ and BAUDRATE in uar.java to suit your clock and desired baud rate. Comments in the code and the testbench uartest show how to use it. The receiver uar can stand alone. The transmitter uat needs the baud4en timing signal output from uar. The testbench uartest just echoes the byte from uar out to uat, and drives its low three bits onto some LEDs. I haven't tested it very much yet, but it seems to work fine. I'm using JHDL 0.3.3, with JDK 1.3.0_02. To compile and netlist it, I javac'd uar.java, uat.java and uartest.java, then 'java jab uartest'. I cycled it once or twice to make sure it has its clock (Russell said to), then typed 'netlist -insertpads t uartest.edf' at the CLI. I compiled with Xilinx Student Edition 2.1i command line ngdbuild, map, par and bitgen. (I use the Cygnus cygwin shell on W98.) I've also attached the uartest.ucf I used with my board. I hope my novice JHDL style isn't too bad. Please have a look and suggest improvements if you are so inclined. JHDL <http://www.jhdl.org> is great. --Mike ---------- // Copyright (C) 2001, Michael Butts // JHDL: Simple fixed baud-rate 4X-sampling UART: Testbench // ----------------------------------------------------------------------------| // This program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public License // as published by the Free Software Foundation; either version 2 // of the License, or (at your option) any later version. // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. // ----------------------------------------------------------------------------| import byucc.jhdl.base.*; import byucc.jhdl.Logic.*; import byucc.jhdl.Xilinx.*; import byucc.jhdl.Xilinx.Virtex.*; public class uartest extends Logic { public static CellInterface[] cell_interface = { in("rs232rx", 1), // Serial input, mark is high out("rs232tx", 1), // Serial output, mark is high out("led_n", 3), // low 3 bits of received character, active low }; public uartest(Node parent, Wire rs232rx, Wire rs232tx, Wire led_n) { super(parent); connect("rs232rx", rs232rx); connect("rs232tx", rs232tx); connect("led_n", led_n); Wire rcv_out = wire(8), new_rcv_out = wire(1); Wire baud4en = wire(1); new uar(this, rs232rx, rcv_out, new_rcv_out, baud4en); Wire ledreg = regce(rcv_out, new_rcv_out); not_o(ledreg.range(2,0), led_n); new uat(this, rcv_out, new_rcv_out, baud4en, rs232tx, nc()); } } ---------- GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. 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If this is what you want to do, use the GNU Library General Public License instead of this License. ---------- // Copyright (C) 2001, Michael Butts // JHDL: Simple fixed baud-rate 4X-sampling UART: Receiver half // ----------------------------------------------------------------------------| // This program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public License // as published by the Free Software Foundation; either version 2 // of the License, or (at your option) any later version. // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. // ----------------------------------------------------------------------------| import byucc.jhdl.base.*; import byucc.jhdl.Logic.*; import byucc.jhdl.Xilinx.*; import byucc.jhdl.Xilinx.Virtex.*; import byucc.jhdl.modgen.*; public class uar extends Logic { static final int CLKFREQ = 30000000; // clk frequency in Hz // static final int CLKFREQ = 300000; // clk frequency in Hz for jab static final int BAUDRATE = 9600; // Receiver and transmitter baud rate public static CellInterface[] cell_interface = { in("rcvr", 1), // serial receive input, mark is high out("rcv_out", 8), // receive output register out("new_rcv_out", 1), // high one clk cycle when rcv_out loaded out("baud4en", 1) // for uat: true for one clk cycle at 4X baud rate }; public uar(Node parent, Wire rcvr, Wire rcv_out, Wire new_rcv_out, Wire baud4en) { super(parent); connect("rcvr", rcvr); connect("rcv_out", rcv_out); connect("new_rcv_out", new_rcv_out); connect("baud4en", baud4en); //------Common Timing for uar and uat------------------------------------------ int clkdivcycs = CLKFREQ/(BAUDRATE*4); // clkdiv cycle // clkdivw is bitwidth needed for clkdiv counter int clkdivw = (int) Math.ceil(Math.log(clkdivcycs) / Math.log(2)); Wire clkdiv = wire(clkdivw); // upcnt: ce, load, data in, data out new upcnt(this, vcc(), baud4en, constant(clkdivw,0), clkdiv, "clkdiv"); // baud4en is true for one clk cyc at 4X the baud rate nor_o(xor(clkdiv, constant(clkdivw, clkdivcycs)), baud4en); //------Receiver--------------------------------------------------------------- // Receiver state machine, only changes state on baud4en Wire rstart = wire(1), rrun = wire(1), ridle = wire(1), // the states rfinish = wire(1); // exits ridle // rstart is active for one cycle when rcvr goes low (space) regce_o(and(ridle, not(rcvr)), baud4en, rstart, "rstart"); // rrun is on for 36 cycles after rstart regce_o(or(and(rstart, not(rcvr)), and(rrun, not(rfinish))), baud4en, rrun, "rrun"); // Delay rrun 1 clk cycle for new_rcv_out Wire rrunq = reg(rrun); and_o(rrunq, not(rrun), new_rcv_out); // 1 clk cyc when rrun falls // Otherwise idle regpe_o(or(and(ridle, rcvr), // stay idle if rcvr is high and(rstart, rcvr), // idle if rcvr goes high in rstart and(rrun, rfinish), // idle when finished and(not(ridle), not(rstart), not(rrun)) ), // init baud4en, ridle, "ridle"); // Count rrun cycles to control reception Wire rcvctr = wire(6); // rcvctr = if ridle: 0, else if rrun: rcvctr+1, else hold Wire rcvctr_load = and(ridle, baud4en); Wire rcvctr_count = and(rrun, baud4en); // upcnt: ce, load, data in, data out new upcnt(this, or(rcvctr_load, rcvctr_count), rcvctr_load, constant(6,0), rcvctr, "rcvctr"); // rfinish: go to ridle when rcvctr == 35 nor_o(xor(rcvctr, constant(6,35)), rfinish, "rfinish"); // receiver shift register Wire rcvsr_en = and(rrun, nor(rcvctr.range(1,0))); // every 4th cycle Wire rcvsr = wire(8); regce_o(concat(rcvr, rcvsr.range(7,1)), and(baud4en, rcvsr_en), rcvsr, "rcvsr"); // receiver output register regce_o(rcvsr, rfinish, rcv_out); } } ---------- // Copyright (C) 2001, Michael Butts // JHDL: Simple fixed baud-rate UART: Transmitter half // ----------------------------------------------------------------------------| // This program is free software; you can redistribute it and/or // modify it under the terms of the GNU General Public License // as published by the Free Software Foundation; either version 2 // of the License, or (at your option) any later version. // This program is distributed in the hope that it will be useful, // but WITHOUT ANY WARRANTY; without even the implied warranty of // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // GNU General Public License for more details. // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. // ----------------------------------------------------------------------------| import byucc.jhdl.base.*; import byucc.jhdl.Logic.*; import byucc.jhdl.Xilinx.*; import byucc.jhdl.Xilinx.Virtex.*; import byucc.jhdl.modgen.*; public class uat extends Logic { public static CellInterface[] cell_interface = { in("xmt_in", 8), // transmit input data in("load_xmt_in", 1), // high one clk cycle to load and transmit in("baud4en", 1), // timing signal from uar out("xmtr", 1), // serial transmit output, mark is high out("xmt_rdy", 1), // transmit input register may be loaded }; public uat(Node parent, Wire xmt_in, Wire load_xmt_in, Wire baud4en, Wire xmtr, Wire xmt_rdy) { super(parent); connect("xmt_in", xmt_in); connect("load_xmt_in", load_xmt_in); connect("baud4en", baud4en); connect("xmtr", xmtr); connect("xmt_rdy", xmt_rdy); // transmit divide-by-4 to control shift out Wire xmtdiv = wire(2); // upcnt: ce, load, data in, data out new upcnt(this, baud4en, gnd(), constant(2,0), xmtdiv, "xmtdiv"); Wire bauden = and(nor(xmtdiv), baud4en); // one clk cyc 1X baud rate // Loading the new character loads the down counter with 0xF Wire load_xmtsr = and(load_xmt_in, xmt_rdy); // Then shift it out at the baud rate Wire shift_xmtsr = and(bauden, not(xmt_rdy)); // Down counter controls transmission Wire xmtctr = wire(4); new downcnt(this, or(load_xmtsr, shift_xmtsr), // ce load_xmtsr, // load constant(4,0xF), // load data xmtctr, 0, "xmtctr"); // reset to 0 // Ready output is true when this counter is 0 nor_o(xmtctr, xmt_rdy); // Transmitter shift register Wire xmtsr = wire(10); regc_o(mux(mux(xmtsr, // hold concat(vcc(), xmtsr.range(9,1)), // shift down shift_xmtsr), concat(vcc(), xmt_in, gnd()), // load load_xmtsr), xmtsr, "xmtsr"); // Last bit of SR is xmtr, resets to 1 to hold it at mark when idle regp_o(mux(mux(xmtr, // hold xmtsr.gw(0), // shift in shift_xmtsr), vcc(), // load load_xmtsr), xmtr, "xmtr"); } } [Non-text portions of this message have been removed] |