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Discussion Groups | FPGA-CPU | RE: xr16vx in JHDL is running on chip
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
xr16vx in JHDL is running on chip - Mike Butts - Jun 10 15:54:00 2001
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I have my implementation of xr16 in JHDL running reliably on my Insight XC2S100 board. It's running a C program which is echoing serial in to serial out, and also to LEDs and a 7-seg LCD. It also has passed Jan's xr16.s diagnostics live on the chip as well as in simulation. In its current form, it's a 16-bit microcontroller, completely contained in the FPGA, including 1KB or 4KB or BlockRAM main memory, serial UART, timer, and a couple of parallel ports. With only modest effort PAR settings, it's good for 35 MHz. Most instructions are a single cycle, loads and taken branches are two. I have tilted towards simplicity and clarity in this design, rather than absolute minimum size and maximum speed, as Jan did in his schematic implementation. It's aimed at the Virtex/Spartan-II architecture, using dual-ported BlockRAMs for main memory, dual-ported CLB RAMs for registers, and using and/or rather than tri-state TBUFs for the system read data bus. In JHDL, it all fits in 355 slices, comparable to 335 XC4000 CLBs, which is 29% of the XC2S100. XR16 is a 16-bit RISC ISA developed by Jan Gray, and available for non-commercial use at http://www.fpgacpu.org. He wrote an excellent three-part Circuit Cellar article series, and has prepared very complete documentation, including an ISA Spec. Best of all, he ported LCC to xr16, so the package includes a full ANSI C compiler. JHDL is available at http://www.jhdl.org. "JHDL is a set of FPGA CAD tools developed at BYU that allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist and interface with back-end tools for synthesis, and so forth. It is an exploratory attempt to identify the key features and functionality of good FPGA tools." Briefly, JHDL is a set of Java classes, which you can use in a Java program to describe your design. I call it "constructive" design. Higher-level, but not synthesized. You have excellent control over the implementation from the JHDL source, including placement. The 'jab' tool is great. You can easily simulate and testbench your design iteractively with waveforms in jab, then netlist it to EDIF. I've really enjoyed using it. I believe I'm getting better size and speed than I did with Verilog and the FPGA Express 3.4 in the Xilinx Student Edition. Details of the result are below. I have written some perl scripts to compile C code, and convert the hex into init files which are read by the JHDL Java for the main memory in jab, and thus included in the EDIF. So the C-to-execution flow requires jab to netlist and a full Xilinx flow, which only takes a couple of minutes. The software is in the bitstream, so xr16vx and its application just come up running at FPGA config. I want to do just one more thing, and that's write a primitive debugger which can read hex files directly into main memory. Then SW development can proceed without the JHDL and Xilinx tools. Then I'll release the JHDL source under the GPL and post it all on the web. Maybe in a week or two. I have found several bugs in my old Verilog and have generally improved the implementation. I may fold them back into Verilog and release xr16vx in that form too. But I'm using JHDL exclusively in my at-home FPGA research now. --Mike Target Device : x2s100 Target Package : pq208 Target Speed : -5 Mapper Version : spartan2 -- D.22 Mapped Date : Sun Jun 10 12:13:46 2001 Design Summary -------------- Number of errors: 0 Number of warnings: 10 Number of Slices: 355 out of 1,200 29% Number of Slices containing unrelated logic: 0 out of 355 0% Number of Slice Flip Flops: 199 out of 2,400 8% Total Number 4 input LUTs: 605 out of 2,400 25% Number used as LUTs: 541 Number used for Dual Port RAMs: 64 (Two LUTs used per Dual Port RAM) Number of bonded IOBs: 26 out of 140 18% Number of Block RAMs: 2 out of 10 20% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25% Number of RPM macros: 27 -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- NET "ibufg_clk_in" PERIOD = 33 nS HIGH | 33.000ns | 28.089ns | 13 50.000 % | | | -------------------------------------------------------------------------------- |
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RE: xr16vx in JHDL is running on chip - Jan Gray - Jun 10 16:44:00 2001
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Very well done, Mike! I can hardly wait to read more. One can floorplan in JHDL, can't one? For you JHDL folks, greetings, visit www.fpgacpu.org/xsoc/index.html for a link to the XSOC kit which includes the xr16 specs, tests, and C compiler and assembler, as well as the old pipelined schematic and Verilog implementations of xr16. (BTW, I am about to take a fresh look at jbits.) Jan Gray, Gray Research LLC |
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Variable speed 3 phase asy. Induction motor PWM genetartor - Fernando - Jun 10 17:06:00 2001
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Dear all I am going to design whole project of my MS teases on Variable speed 3 phase asy. Induction motor PWM genetartor or "frequency inverter with IGBT" with FPGA. Please let me know if any prior work has been done and is there any related document available. This would help my documents and final work be better presented and proable errors be fixed in my own version. Best regrds Fernando __________________________________________________ |
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