This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
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I've polished off the xr16vx microcontroller in JHDL, and posted it, along with tools, tests and documentation: http://www.easystreet.com/~mbutts/xr16vx_jhdl.html xr16vx is a 16-bit microcontroller design for FPGAs, which I've released as open source programming under the GPL. Including memory, serial and parallel ports and a timer, it fits in only 29% of a Xilinx Spartan-II XC2S100-5, at up to 39 MHz. xr16vxcpu implements the xr16 16-bit RISC instruction set architecture of Jan Gray: http://www.fpgacpu.org/xsoc/README.html Jan's xsoc package includes an assembler and ANSI C compiler for xr16 based on lcc. My xr16vxcpu runs at one cycle per instruction, except taken branches and loads used next cycle. It takes advantage of the dual-ported BlockRAM to fetch instructions and data in parallel. xr16vx is written in JHDL, a set of Java classes and tools for FPGA design developed at BYU: http://www.jhdl.org/release-latest/docs/overview/intro.html In JHDL you do register-level design but without synthesis. I've found JHDL a very satisfying development environment, and am getting slightly better speed and area than I got in Verilog with FPGA Express. Since the xr16vx microcontroller is completely contained in the FPGA, you can write a C program for xr16vx, init the BlockRAMs with it in the EDIF file, and thus have the application built into the bitstream, executing at power-up. I include some tools I wrote to make doing this easy. Thanks to Jan Gray's xsoc, BYU's JHDL and Xilinx WebPACK ISE, the entire design flow for xr16vx is available on the Web at no cost. I've developed xr16vx myself on my own time, because I love FPGAs and I love CPU design. I hope students, experimenters, and anyone on a limited budget will find xr16vx useful. --Mike |