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Discussion Groups | FPGA-CPU | Revamped Sparrow ISA
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Revamped Sparrow ISA - Author Unknown - Jul 21 1:50:00 2001
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I've revamped the ISA for a 32 bit version of the Sparrow core. If anyone's interested take a look at http://www.birdcomputer.ca/is_toc.html Probably the most notable instructions are 'ret' which is a return and de-allocate, 'cab' compare, add and branch, and 'ran' generate random number. Also supported is indexed addressing. Rob http://www.birdcomputer.ca/ |
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Re: Revamped Sparrow ISA - Ben Franchuk - Jul 21 11:39:00 2001
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wrote: > > I've revamped the ISA for a 32 bit version of the Sparrow core. If > anyone's interested take a look at > http://www.birdcomputer.ca/is_toc.html > Probably the most notable instructions are 'ret' which is a return > and de-allocate, 'cab' compare, add and branch, and 'ran' generate > random number. Also supported is indexed addressing. > > Rob http://www.birdcomputer.ca/ Ok what about ldb/stb load byte/store byte? What about unsigned loads? Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics. |
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Re: Revamped Sparrow ISA - Author Unknown - Jul 21 16:26:00 2001
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--- In fpga-cpu@y..., Ben Franchuk <bfranchuk@j...> wrote: Wow! Thanks for taking the time to have a look. > Ok what about ldb/stb load byte/store byte? > What about unsigned loads? I did not actually forget about these things. I want to discourage the use of bytes. They're not all that useful as a data storage means, and are much more useful for transmitting / recieving data. Since an FPGA is in use, the size of ports for I/O can easily be controlled and it's easy to add hardware for byte serialization. It's also quite easy to use the ISA for byte manipulation. In most cases whether a sixteen bit load is signed or unsigned doesn't make that much difference. Since sign extending is harder to do in software, I opted to provide it in hardware in preference to unsigned loads. It's easy enough to get an unsigned load by simply zeroing out the upper bits of the loaded register (and Rt,Ra,#0xffff). I have thought of adding instructions to the ISA to sign or zero extend from an arbitrary bit position. Having said the above, I do provide some room in the ISA encoding to support byte loads and stores and unsigned loads. I've just rated these instructions as not having the same priority for implementation as the base architecture. I spent a lot of time designing the ISA up front so that it is scalable to a more powerful processor (that is: a SIMD superscaler 16/32/64/128 bit). I plan to extend it, rather than drop the ISA or have some wildly contorted encodings supporting future enhancements. Hopefully, there should be future versions with *binary* compatibility. Rob http://www.birdcomputer.ca > -- > "We do not inherit our time on this planet from our parents... > We borrow it from our children." > "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk > Now with schematics. |
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