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Discussion Groups | FPGA-CPU | RE: XSV Board

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

XSV Board - Steve - Aug 3 8:55:00 2000

Hi all! I recently purchased the new XESS XSV board that contains a Virtex
FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project, but
I'm having some difficulties on trying to modify the design to reflect my
new board.

I was wondering if anyone has already modified the project for the XSV
board or at least modified it enough to handle a 16-bit wide RAM.

Thanks very much for the help,
Steve




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Re: XSV Board - Mike Butts - Aug 3 9:41:00 2000

I'm about 3/4 done with a clean-sheet-of-paper Verilog xr16 for Virtex
that uses Virtex BlockRAMs for instruction and data memories. That
will have the nifty property that an entire (small) application,
including code and data, can be in the FPGA bitstream, so it's
just a component that comes up when you program the FPGA.
Maybe in a month or so I'll have something to share.

A big difference is that Virtex has only got half as many BUFTs
per CLB as XC4000. Jan's design is largely based on having a
BUFT for every LUT or FF output. Virtex designs have to be more
muliplexer-based. It will be interesting to see how the result
compares with Jan's tightly crafted XC4000 version.

I'll keep this maillist posted. In the meantime I encourage
you to take the Verilog version and try to modify it for your
board. That's the whole point of all this!

--Mike

Steve wrote:
>
> Hi all! I recently purchased the new XESS XSV board that contains a Virtex
> FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project, but
> I'm having some difficulties on trying to modify the design to reflect my
> new board.
>
> I was wondering if anyone has already modified the project for the XSV
> board or at least modified it enough to handle a 16-bit wide RAM.
>
> Thanks very much for the help,
> Steve
>
> To Post a message, send it to:
>
> To Unsubscribe, send a blank message to:





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Re: XSV Board - Jamie R. Chinn - Aug 3 14:36:00 2000

I was going to get one of those but they were out of them.
I decided to try a Spartan 2 100k chip.
Insight Electronics has them for $125 soldered onto a development board.
I'll let everyone know what I find when the boards come in.

----- Original Message -----
From: "Steve" <>
To: <>
Sent: Thursday, August 03, 2000 6:55 AM
Subject: [fpga-cpu] XSV Board > Hi all! I recently purchased the new XESS XSV board that contains a
Virtex
> FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project,
but
> I'm having some difficulties on trying to modify the design to reflect my
> new board.
>
> I was wondering if anyone has already modified the project for the XSV
> board or at least modified it enough to handle a 16-bit wide RAM.
>
> Thanks very much for the help,
> Steve > To Post a message, send it to:
>
> To Unsubscribe, send a blank message to:




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Re: XSV Board - Jamie R. Chinn - Aug 3 14:39:00 2000

I would like to try Verilog out but I haven't found a synthesizer/simulator
that I can afford.
Anyone have any Ideas?
Xilinx has a license for $500 that includes Verilog synthesis.
Will that work?
----- Original Message -----
From: "Mike Butts" <>
To: <>
Sent: Thursday, August 03, 2000 7:41 AM
Subject: Re: [fpga-cpu] XSV Board > I'm about 3/4 done with a clean-sheet-of-paper Verilog xr16 for Virtex
> that uses Virtex BlockRAMs for instruction and data memories. That
> will have the nifty property that an entire (small) application,
> including code and data, can be in the FPGA bitstream, so it's
> just a component that comes up when you program the FPGA.
> Maybe in a month or so I'll have something to share.
>
> A big difference is that Virtex has only got half as many BUFTs
> per CLB as XC4000. Jan's design is largely based on having a
> BUFT for every LUT or FF output. Virtex designs have to be more
> muliplexer-based. It will be interesting to see how the result
> compares with Jan's tightly crafted XC4000 version.
>
> I'll keep this maillist posted. In the meantime I encourage
> you to take the Verilog version and try to modify it for your
> board. That's the whole point of all this!
>
> --Mike
>
> Steve wrote:
> >
> > Hi all! I recently purchased the new XESS XSV board that contains a
Virtex
> > FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project,
but
> > I'm having some difficulties on trying to modify the design to reflect
my
> > new board.
> >
> > I was wondering if anyone has already modified the project for the XSV
> > board or at least modified it enough to handle a 16-bit wide RAM.
> >
> > Thanks very much for the help,
> > Steve
> >
> > To Post a message, send it to:
> >
> > To Unsubscribe, send a blank message to: > To Post a message, send it to:
>
> To Unsubscribe, send a blank message to:




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RE: XSV Board - Will Cummings - Aug 3 17:55:00 2000

Hi Jamie,

You can download free Verilog synthesis/simulation tools from Xilinx at

http://www.xilinx.com/sxpresso/webpack.htm

Will Cummings
Xilinx Dedicated FAE
Insight Electronics, Inc.
(425) 576-7503
-----Original Message-----
From: Jamie R. Chinn [mailto:]
Sent: Thursday, August 03, 2000 12:39 PM
To:
Subject: Re: [fpga-cpu] XSV Board I would like to try Verilog out but I haven't found a synthesizer/simulator
that I can afford.
Anyone have any Ideas?
Xilinx has a license for $500 that includes Verilog synthesis.
Will that work?
----- Original Message -----
From: "Mike Butts" <>
To: <>
Sent: Thursday, August 03, 2000 7:41 AM
Subject: Re: [fpga-cpu] XSV Board > I'm about 3/4 done with a clean-sheet-of-paper Verilog xr16 for Virtex
> that uses Virtex BlockRAMs for instruction and data memories. That
> will have the nifty property that an entire (small) application,
> including code and data, can be in the FPGA bitstream, so it's
> just a component that comes up when you program the FPGA.
> Maybe in a month or so I'll have something to share.
>
> A big difference is that Virtex has only got half as many BUFTs
> per CLB as XC4000. Jan's design is largely based on having a
> BUFT for every LUT or FF output. Virtex designs have to be more
> muliplexer-based. It will be interesting to see how the result
> compares with Jan's tightly crafted XC4000 version.
>
> I'll keep this maillist posted. In the meantime I encourage
> you to take the Verilog version and try to modify it for your
> board. That's the whole point of all this!
>
> --Mike
>
> Steve wrote:
> >
> > Hi all! I recently purchased the new XESS XSV board that contains a
Virtex
> > FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project,
but
> > I'm having some difficulties on trying to modify the design to reflect
my
> > new board.
> >
> > I was wondering if anyone has already modified the project for the XSV
> > board or at least modified it enough to handle a 16-bit wide RAM.
> >
> > Thanks very much for the help,
> > Steve
> >
> > To Post a message, send it to:
> >
> > To Unsubscribe, send a blank message to: > To Post a message, send it to:
>
> To Unsubscribe, send a blank message to:
To Post a message, send it to:

To Unsubscribe, send a blank message to:





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Re: XSV Board - Arrigo Benedetti - Aug 4 2:20:00 2000

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Hi all! I recently purchased the new XESS XSV board that contains a Virtex
FPGA and a 16-bit wide SRAM. I am very interested in the XSOC project, but
I'm having some difficulties on trying to modify the design to reflect my
new board.

I was wondering if anyone has already modified the project for the XSV
board or at least modified it enough to handle a 16-bit wide RAM.

Thanks very much for the help,
Steve

I am currently porting the 0.93 version of the processor to VHDL and
I'm also targeting Virtex. This is a pretty much a straight port, the
only optimization being going from a bytewide external RAM to a couple
of Virtex BlockRAM connected to the internal 16 bit data bus.
I am very happy to make all the code available, but since this code is
derived from Jan's work I've asked him to consider the issues related
to licensing of third party contributions before I make it public.

Best,

-Arrigo
--
Dr. Arrigo Benedetti e-mail:
Caltech, MS 136-93 phone: (626) 395-3695
Pasadena, CA 91125 fax: (626) 795-8649





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