XSOC in Verilog and perhaps VHDL | FPGA-CPU

Hi Jan, My really interest in the VHDL is to learn it (i'm still a newbie with VHDL) and practice with this interesting project... I don't use Verilog, but I know some of the sintax and I think will be able to understand it... I will try to do the same with VHDL if you share the Verilog code with me :-) ... by the way, I will be one of the beta testers of the Verilog code. Thanks. Hern�n S�nchez Analista de Telecomunicaciones SURATEP > -----Mensaje original----- > De: Jan Gray, Gray Research LLC [SMTP:] > Enviado el: Viernes, 17 de Marzo de 2000 03:23 p.m. > Para: > Asunto: [fpga-cpu] XSOC in Verilog and perhaps VHDL > > > From: Hernan Dario Sanchez Echeverri [mailto:] > > > some idea > > doing this using VHDL ? I would like to help in any way. > > Thanks for your kind words and your interest. > > There is a Verilog version of the XSOC Project, including xr16. It needs > a > little more polish, documentation, and testing before I add it to the XSOC > Project Distribution. I hope to release it for beta testing approximately > April 1. > > Assuming there was a Verilog version, would that be acceptable to you, or > do > you have a requirement to use VHDL? How to people feel about Verilog vs. > VHDL? I am more fluent in Verilog (although still a newbie), than VHDL, > and > prefer it to VHDL. I do understand there are some facilities in VHDL that > are missing in Verilog. > > I am also looking forward to using a synthesis tool that supports RLOCs > and > FMAPs. Unfortunately FPGA Express (provided in Xilinx Student Ed.) does > not > (see http://www.fpgacpu.org/usenet/rope_pushing.html), and I have had to > resort to partial floorplanning through program generated UCF files. > > For your interest here is a message comparing the schematic version to the > Verilog version. > > <<< > From: Jan Gray > Sent: Wednesday, February 09, 2000 3:21 PM > Subject: ... comparing schematic to Verilog version > > ... > Now that we have the design running properly in Verilog, let's compare the > schematic to the Verilog+explicitly floorplanned registers version. > Target > XC4005XLPC84C-3. Effort level 5/5 on both. Identical timing specs except > clock frequency goal. > > What Sch'c Verilog > ---- ----- ------- > Cycle time 41 53 ns > Freq 24.5 18.9 MHz > Flops 252 252 > 4LUTs 263 288 > ROMs 21 0 > Total FGs 284 288 > 3LUTs 40 48 > RAMs 64 64 > TBUFs 152 152 > P&R time 5'45" 8'52" > > Commentary: here, the Verilog doesn't fare too badly. 25% slower, > approximately the same area. Of course, I took great care in coding the > Verilog, examining the output to make sure no extraneous logic was > introduced, and applied as much floorplanning as was practical (e.g. > registers and RAMs). > ... > >>> > > Jan Gray > Gray Research LLC >

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Re: XSOC in Verilog and perhaps VHDL - Hernan Dario Sanchez Echeverri - Mar 17 15:45:00 2000