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Discussion Groups | FPGA-CPU | RE: Timings

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Re: Timings - Ben Franchuk - Oct 16 23:11:00 2001

wrote:
>
> I'm thinking of implementing a (small 64 entry) d-cache in LUT ram
> because routing for a block ram is too slow for single cycle access.
> I'm getting wildly different timings between synthesis and PAR. After
> mapping, the tools report the design should run >95MHz, however after
> PAR the reports say 24MHz. The delay reported in PAR is 41ns, 4.7ns
> of this is logic and the other 37ns (89%) is for routing.
>
> Do you think it's possible to get this working >50MHz after
> floorplanning, or is it not worth the effort ?
>
> Thanks
> Rob

Get it working first then tweek it for speed. Ben.
--
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.


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Timings - Author Unknown - Oct 18 21:07:00 2001

I'm thinking of implementing a (small 64 entry) d-cache in LUT ram
because routing for a block ram is too slow for single cycle access.
I'm getting wildly different timings between synthesis and PAR. After
mapping, the tools report the design should run >95MHz, however after
PAR the reports say 24MHz. The delay reported in PAR is 41ns, 4.7ns
of this is logic and the other 37ns (89%) is for routing.

Do you think it's possible to get this working >50MHz after
floorplanning, or is it not worth the effort ?

Thanks
Rob





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Direction of soft core cpu's (Re: Timings) - Author Unknown - Oct 18 23:34:00 2001

--- In fpga-cpu@y..., Ben Franchuk <bfranchuk@j...> wrote:
>
> Get it working first then tweek it for speed. Ben.
> --
> Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
> "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
> Now with schematics.

Thanks for the good advice. "Tweaking for speed" perhaps wasn't a
good term to use. I'm more or less gaining experience with the FPGA
characteristics by experimentation, trial and error.

I've come to the conclusion I'm worrying too much about obtaingin
high performance for a specific implementation. It's probably better
to just be satisfied with good performance from a *simple*, sound
architecture.

Future compatibility (implemented in any technology) is probably more
important the performance of a specific implementation.

Rob




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RE: Timings - Jan Gray - Oct 19 12:01:00 2001

> Do you think it's possible to get this working >50MHz after
> floorplanning, or is it not worth the effort ?

I can't speak for Virtex-II, with its active (buffered) interconnect
fabric, which gets most nets down to <2 ns delays, but for XC4000X and
Virtex/E, floorplanning can certainly halve critical path net delays,
and, as importantly, make the delays predictable so you have terra firma
upon which to make methodical implementation decisions.

Hand-in-hand with floorplanning is a certain amount of careful
technology mapping: structuring your design so critical paths map into a
small number of 4-LUT logic levels.

Jan Gray, Gray Research LLC




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RE: Timings - Ed Corter - Oct 19 12:25:00 2001


--- Jan Gray <> wrote:
> > Do you think it's possible to get this working
> >50MHz after
> > floorplanning, or is it not worth the effort ?
>
> I can't speak for Virtex-II, with its active
> (buffered) interconnect
> fabric, which gets most nets down to <2 ns delays,
> but for XC4000X and
> Virtex/E, floorplanning can certainly halve critical
> path net delays,
> and, as importantly, make the delays predictable so
> you have terra firma
> upon which to make methodical implementation
> decisions.
>
> Hand-in-hand with floorplanning is a certain amount
> of careful
> technology mapping: structuring your design so
> critical paths map into a
> small number of 4-LUT logic levels.
>
> Jan Gray, Gray Research LLC > To Post a message, send it to:
> To Unsubscribe, send a blank message to:
>
>
>
I have alot of experience with the VirtexE

Please email me the info on what synhtesis tool and
what version of mapper / Place and rount is being used
and any timing constraints bneing used
we have sucsussfully done an OFDM modem desing that
spanned 4 1000E's and ran at 93.333 mHz using
SynplifyPro for synthesis and constraint generation.

__________________________________________________


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Re: Timings - Author Unknown - Oct 19 20:50:00 2001

--- In fpga-cpu@y..., Ed Corter <artiedc@y...> wrote: > Please email me the info on what synhtesis tool and
> what version of mapper / Place and rount is being used
> and any timing constraints bneing used
>
> artiedc@y...
>
First, I made a boo-boo. I was looking at the wrong timing report.
Tools report my design will work at 56MHz not 95MHz (I kind of
wondered the design being in a -5 SpartanII). That kind of explains
most of the difference, although it still quite a step down to 25MHz
after PAR.

I'm using the tools provided with Webpack 4.1 (XST). Are there any
other good free tools out there ?

I'd like to make my design available somehow (".edn" format ?) when I
finish. If I floorplan the design is it possible retain the
floorplanning in the .edn file ?






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Re: Re: Timings - Ed Corter - Oct 19 21:51:00 2001


--- wrote:
> --- In fpga-cpu@y..., Ed Corter <artiedc@y...>
> wrote:

I'm using the tools provided with Webpack 4.1 (XST).
Are there any
other good free tools out there ?

Thats the same that I use at home; however, I batch
execute all steps of the build.. except the verilog
compile is still done with ise GUI.

I'd like to make my design available somehow (".edn"
format ?) when I
finish. If I floorplan the design is it possible
retain the
floorplanning in the .edn file ?

Answer is yes..
In the IDE there is an option for creatin a Macro. The
macro retains the loc's and routing.
When a macro is being instantiated into another
design it must not have the IO buffers: just net
ports. Also the Macro serach path must be provided at
build time.

===== __________________________________________________





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