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Discussion Groups | FPGA-CPU | RE: Re: Latching LUT ram outputs
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
RE: Re: Latching LUT ram outputs - Ed Corter - Nov 6 14:40:00 2001
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wrote: Talking about chipscope .. I would like to know if anybody on this group has been able to get the following combination working for Chipscope: Xilinx Foundation 3.1i Xess v1.0 carrying a XCV800 Chipscope Port - parrallel/JTAG/Xcheqer/ anything will do ... Saurav. NTU-Singapore I have used ChipScope with the XCV1000E's If you are still having problems feel free to email me. I had to write a paper on how to use it because the Xilinx FAE's confused everybody where I worked. To be honest the FAE's were confused. Ed Corter Speaking of FPGA CPU's .... I just now returned from an Altera seminar on 2 new products. 1 is a FPGA with ARM core on the same die. 2. is called NIOS and is a configurable instantiatable Microprocessor core. Very Cool ! __________________________________________________ |
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