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Discussion Groups | FPGA-CPU | Assigning a three-state to the pad buffer
This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Assigning a three-state to the pad buffer - Filip Miletic - Nov 16 4:31:00 2001
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Hello all. I have the following problem making the Xilinx i2c interface synthesize on XC4010XL. Namely I wrote a wrapper function which encompasses the Xilinx i2c core and adjusts it to the 8051 bus. I have a problem assigning the SDA and SCL bidirectional lines that come out of the i2c entity to the output pad drivers. I have no enable signal coming out of i2c so I cannot make the three-state in the top level entity. Apparently this is the reason the whole SDA and SCL nets get optimized out of the design. Is there a portable way to tell the synthesizer pair (Synplicity+Xilinx design manager) to propagate the internal 3-state driver which of course are present inside the core to be assigned to the 3-state on the output pad? If I synthesize the i2c core alone, it being the top level entity, this problem does not arise. TIA, f. __________________________________________________ |
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Re: Assigning a three-state to the pad buffer - Filip Miletic - Nov 16 5:12:00 2001
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--- In fpga-cpu@y..., Filip Miletic <filipmiletic@y...> wrote: > nets get optimized out of the design. By the way, could someone at least point out why the pins could get optimized out? TIA, f. |
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