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Discussion Groups | FPGA-CPU | Need Help of Performance Enhancement

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Need Help of Performance Enhancement - Anand Gopal Shirahatti - Dec 1 17:46:00 2001


Hi all,
Actually we are designing a CISC processor on Altera fpga in 10ke family.
We are facing problem with the speed.We want the processor to run at 40Mhz.But it is not doing so.If anybody who has pre working knowledge on using the altera 10ke family for simillar applications, Guide us please in this direction.
I would like it know if it is worth trying modifying the architecture or is it not possible with this family of fpga to run CISC at 40Mhz.
Any suggestions and opinion shall be apperciated.
Thanks in advance.
Anand.




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RE: Need Help of Performance Enhancement - Eugene Fleisher - Dec 1 17:52:00 2001

If you are using internal memory it should run 40 MHz, but if the memory
outside then just going through I/O will not allow you to run faster then
32MHz or so. We did it for the embedded 8051 design...

Just for your information here is the site wher you can get replacement for
the ByteBlaster but this one will work with any voltage of the FPGA/EPLD I/O
from 1.8 V to 5.5 V

http://www.nefdesign.com

Thanks,

Eugene

-----Original Message-----
From:

.com
[mailto:
ps.yahoo.com]On Behalf Of Anand Gopal Shirahatti
Sent: Saturday, December 01, 2001 2:46 PM
To:
Subject: [fpga-cpu] Need Help of Performance Enhancement
Hi all, Actually we are designing a CISC processor on Altera fpga in 10ke
family. We are facing problem with the speed.We want the processor to run at
40Mhz.But it is not doing so.If anybody who has pre working knowledge on
using the altera 10ke family for simillar applications, Guide us please in
this direction. I would like it know if it is worth trying modifying the
architecture or is it not possible with this family of fpga to run CISC at
40Mhz. Any suggestions and opinion shall be apperciated. Thanks in advance.
Anand. To post a message, send it to:
To unsubscribe, send a blank message to:





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Re: Need Help of Performance Enhancement - Ben Franchuk - Dec 1 19:44:00 2001

Anand Gopal Shirahatti wrote:
> Hi all,
> Actually we are designing a CISC processor on Altera fpga in 10ke family.
> We are facing problem with the speed.We want the processor to run at 40Mhz.But it is not doing so.If anybody who has pre working knowledge on using the altera 10ke family for simillar applications, Guide us please in this direction.
> I would like it know if it is worth trying modifying the architecture or is it not possible with this family of fpga to run CISC at 40Mhz.
> Any suggestions and opinion shall be apperciated.
> Thanks in advance.

Don't look at me -- the best I can do is 17 Mhz, in a EPF10K10LC84-4.
Mind you I have 93% of the 576 CLB's filled. However I have had make
several speed/size trade offs to get the design to fit in the FPGA
thus in a larger FPGA it could run faster.
One thing I have found is you have to watch the number of interconnects,
once it runs out of fast routing lines it really slows down. Also it can
be sensitive
as well for I/O placement. Counters and adders can take up more cells
than one expects as they require buffering of the fast carry lines.

This is true of all FPGA design -- they suck at random logic. The key is
to know the FPGA architecture and the CISC architecture you are working
with. How well they mesh together will give you a idea of the speed
possible.
From what little ( very little that is ) I have done in FPGA's seem to
lay speed wise in 74Sxx and 74ALSxx range for the slowest speed chips.
How ever the only real way to know for sure is to lay out the design.

--
Ben Franchuk --- Pre-historic Cpu's --
www.jetnet.ab.ca/users/bfranchuk/index.html





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RE: Need Help of Performance Enhancement - Perez Ramas, Javier Basilio - Dec 3 2:38:00 2001

Hi!

> -----Mensaje original-----
> De: Anand Gopal Shirahatti [mailto:]
> Enviado el: sábado 1 de diciembre de 2001 23:46
> Para:
> Asunto: [fpga-cpu] Need Help of Performance Enhancement >
> Hi all,
> Actually we are designing a CISC processor on Altera fpga in
> 10ke family.
> We are facing problem with the speed.We want the processor to
> run at 40Mhz.But it is not doing so.If anybody who has pre
> working knowledge on using the altera 10ke family for

Many times a slow speed is due to big combinational paths. Pipelining the
design may help you a lot.

Bye,
Javier Basilio Pérez Ramas





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