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Discussion Groups | FPGA-CPU | Re: Strict P&R in Xilinx chips

This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).

Strict P&R in Xilinx chips - Eric Laforest - Dec 2 22:37:00 2001


Is it possible to generate a design that is explicitely placed and routed?
(ie: this reg goes here, uses these tristate lines up to here, etc...)

I presume that this is not possible with Verilog without a ridiculous
amount of constraint specifications.

Is there a way to do so with what's available with WebPack?

I'm asking this because I have a stack-machine cpu design. It's inherently
not a pipeline and so (I figure) does not map well at all onto a Virtex-II
using the usual methods. I think it would work better if I could precisely
lay out where each register is and which interconnects are used.

Eric LaForest




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Re: Strict P&R in Xilinx chips - Author Unknown - Dec 3 16:54:00 2001

Eric Laforest <> writes:

> Is it possible to generate a design that is explicitely placed and routed?
> (ie: this reg goes here, uses these tristate lines up to here, etc...)
>
> I presume that this is not possible with Verilog without a ridiculous
> amount of constraint specifications.
>
> Is there a way to do so with what's available with WebPack?

Using the tools in WebPack, you can explicitly place but not
explicitly route; you do this using "a ridiculous amount of constraint
specifications".

I would recommend looking into JHDL (www.jhdl.org). This will let you
write Java code which generates and places your CPU design; your Java
program, in conjunction with JHDL, generates an EDIF file which
inserts into the middle of the WebPack design flow.

If you really want to do all your own placing and routing, you should
look into JBits. This Xilinx tool lets you write Java programs to
manipulate Xilinx bitstreams; you then have total control over placing
and routing. It used to be fairly difficult to get a copy of JBits,
but I think recently they've been making copies available to anybody
who asks for one at .

> I'm asking this because I have a stack-machine cpu design. It's inherently
> not a pipeline and so (I figure) does not map well at all onto a Virtex-II
> using the usual methods. I think it would work better if I could precisely
> lay out where each register is and which interconnects are used.

I'm far from an expert on this -- I've never done much with explicit
placement -- but my impression is that it's quite difficult to beat
the Xilinx tools on low-level placement of unstructured logic, and
that it's only worth the effort of explicit placement on larger
structured pieces like datapaths. (Hopefully someone will correct me
if I'm wrong.) If that's true, then you might be able to get the
benefit you want with a reasonably small number of constraints.

Hope this helps.

Carl Witty





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