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This list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project (see http://www.fpgacpu.org/xsoc).
Newbie - nexsyscorp - Dec 15 10:49:00 2001
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Hello, How do you design using FPGA ? How do you determine if you would like to use Altera or Xilinx ? How do you program your post-synthesis PAR onto a chip ? What type of PCB boards do you use to design with FPGA ? Will PAR automatically assign the I/O pins for you ? |
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Have a look at the new TI MCU Center on EmbeddedRelated.com!
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Re: Newbie - Philip Freidin - Dec 16 5:56:00 2001
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On Sat, 15 Dec 2001 15:49:20 -0000, you wrote: >Hello, > >How do you design using FPGA ? Get a copy of the free tools from the Xilinx website called WebPack. Get a book on Verilog at your local book store. Read the book, and go to it. >How do you determine if you would like to use Altera or Xilinx ? Choose Xilinx. >How do you program your post-synthesis PAR onto a chip ? Use a download cable. Connects from the Parallel port of your PC to the chip. Schematic for it is on Xilinx's web site. http://www.xilinx.com/support/programr/files/0380507.pdf >What type of PCB boards do you use to design with FPGA ? Get a board from Xess or Burched. http://www.xess.com/ http://www.burched.com.au/ >Will PAR automatically assign the I/O pins for you ? Yes, or you can select which ones for each signal. ================= Philip Freidin |
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Re: Newbie - Ben Franchuk - Dec 16 12:02:00 2001
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Philip Freidin wrote: > >How do you determine if you would like to use Altera or Xilinx ? > Choose Xilinx. why? I say unless you need a feature of a specific vender pick what software you are most conformable with or have access to. Xilinx is the most popular brand but they are not the only FPGA people. > Use a download cable. Connects from the Parallel port of your PC > to the chip. > Get a board from Xess or Burched. Burch I know gives a download cabe with the kit! > > >Will PAR automatically assign the I/O pins for you ? > Yes, or you can select which ones for each signal. I say select the pins your self, this way you will not have problems with the software deciding to move them on you. -- Ben Franchuk --- Pre-historic Cpu's -- www.jetnet.ab.ca/users/bfranchuk/index.html |
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Re: Newbie - Leon Heller - Dec 16 13:08:00 2001
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>From: Ben Franchuk <> >Reply-To: >To: >Subject: Re: [fpga-cpu] Newbie >Date: Sun, 16 Dec 2001 10:02:30 -0700 > >Philip Freidin wrote: > > >How do you determine if you would like to use Altera or Xilinx ? > > Choose Xilinx. >why? >I say unless you need a feature of a specific vender >pick what software you are most conformable with or have >access to. Xilinx is the most popular brand but they are not >the only FPGA people. > > > Use a download cable. Connects from the Parallel port of your PC > > to the chip. > > Get a board from Xess or Burched. > >Burch I know gives a download cabe with the kit! > > > > >Will PAR automatically assign the I/O pins for you ? > > Yes, or you can select which ones for each signal. >I say select the pins your self, this way you will not >have problems with the software deciding to move them >on you. It might be best to have the PAR select the pins, to minimise delays and so on. They can always be locked later. In fact, the Altera software suggests this the first time a design is compiled. Leon -- Leon Heller, G1HSM Tel: +44 1327 359058 Email: My web page: http://www.geocities.com/leon_heller My low-cost Altera Flex design kit: http://www.leonheller.com _________________________________________________________________ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp. |
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Have a look at the new TI MCU Center on EmbeddedRelated.com!
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Re: Newbie - nexsyscorp - Dec 16 13:17:00 2001
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Thanks a lot for helping me. How do you deal with cores when you want to convert to ASIC ? Are all cores encrypted somehow ? How to they work ? You instantiate a block box, and your simulator/implementor will understand ? Xilinx has logicoresor something called logiblox or coregen. I haven't used them. ALtera has something called Megafunction. Mentor has, I think, Inventra core or somthing like that. I really want to understand how the process work, using cores in your design. |
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Re: Newbie - nexsyscorp - Dec 16 13:42:00 2001
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I like XESS site. :-) Say if you want to build Data Acquisition board, all you really need is sample 2 mega samples per second, storing in buffer, and tell the PC to fetch through a PCI interface (a separate chip), which FPGA chip could you use ? Which ones is faster, distributed RAM or block RAM ? Is there a way to tell the FPGA chip which type of RAM to use ? Or the Place and Route mechanism will do this automatically ? In hoping that you won't be bored with these beginner's questions. Thanks |
Have a look at the new TI MCU Center on EmbeddedRelated.com!
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JTAG help me please !!!! : | ----> : ( - Ed Corter - Dec 16 17:02:00 2001
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Hello all, I am attempting to config aVirtex decice with Xilinx's Paralell programer cable... I am not sure if I have missied any of the "care and feeding requirements for the JTAG port signals.. I.E. pull up's or down's ! I dont have a data sheet with me and my connection is tooooo slow to down load from Xilinx.. So if anyone has this info handy please respond ! Thanks Ed --------------------------------- |
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